Single Shockley Stacking Faults in As-Grown 4H-SiC Epilayers

2010 ◽  
Vol 645-648 ◽  
pp. 327-330 ◽  
Author(s):  
Jawad ul Hassan ◽  
Peder Bergman
Keyword(s):  
Temperature Dependence ◽  
Optical Microscopy ◽  
Optical Spectrum ◽  
Carrier Lifetime ◽  
Geometrical Structure ◽  
Stacking Faults ◽  
Stacking Fault ◽  
Structural Defects ◽  
Forward Voltage ◽  
Substrate Interface

An extended structural defects which locally drastically reduces the carrier lifetime, has been observed in as-grown epilayers. A combination of back polishing, etching in molten KOH and optical microscopy revealed the geometrical structure of the stacking fault inside the epilayer. The fault started close to the epi-substrate interface, expanded initially rapidly but changed geometry after some time and reduced in size during further growth. The optical spectrum as well as the temperature dependence from this fault is identical to the emission from the single Shockley stacking faults previously only observed and formed in the bipolar diodes during forward voltage operation.

Optical and Structural Properties of In-Grown Stacking Faults in 4H-SiC Epilayers

2010 ◽  
Vol 645-648 ◽  
pp. 307-310 ◽  
Author(s):  
Jawad ul Hassan ◽  
Anne Henry ◽  
Peder Bergman
Keyword(s):  
Optical Properties ◽  
Optical Spectrum ◽  
Laser Excitation ◽  
Stacking Faults ◽  
Luminescence Spectra ◽  
Structural And Optical Properties ◽  
Forward Voltage ◽  
Optically Detected ◽  
Low Temperature Photoluminescence ◽  
Epilayer Surface

Two different and novel in-grown triangular stacking faults have been observed and characterized in 4H-SiC epitaxial layers grown on 4o off-cut substrates. The faults were formed at the beginning of the growth and extended continuously in size during the growth. Their structural and optical properties were however different as seen from both synchrotron white beam topography and low temperature photoluminescence. The luminescence spectra were similar but appeared in different energy regions 2.85 – 2.95 eV and 2.48 – 2.64 eV, respectively. BPDs present in the epilayer are found to be transformed into SFs under laser excitation during high resolution optically detected lifetime mapping. The faults are found to expand from the epilayer surface towards the epi-substrate interface. The optical spectrum from this fault is identical to the emission from the single layered Shockley stacking faults with excitonic bandgap of 3.034 eV previously only observed and formed in the bipolar diodes during forward voltage operation.

scholarly journals Effect of multiple laser shock processing on nano-scale microstructure of an aluminum alloy

2018 ◽  
Author(s):  
Simge GencalpIrizalp ◽  
Nursen Saklakoglu
Keyword(s):  
Stacking Faults ◽  
Stacking Fault ◽  
Structural Defects ◽  
Laser Shock ◽  
X Ray Diffraction ◽  
Laser Shock Processing ◽  
Alloy Plate ◽  
X Ray ◽  
Nano Scale ◽  
Shock Processing

In this study, nano-scale microstructural evolution in 6061-T6 alloy after laser shock processing (LSP) were studied. 6061-T6 alloy plate were subjected to multiple LSP. The LSP treated area was characterized by X-ray diffraction and the microstructure of the samples was analyzed by transmission electron microscopy. Focused Ion Beam (FIB) tools were used to prepare TEM samples in precise areas. It was found that even though aluminum had high stacking fault energy, LSP yielded to formation of ultrafine grains and deformation faults such as dislocation cells, stacking faults. The stacking fault probability (PSF) was obtained in LSP-treated alloy using X-Ray diffraction. Deformation induced stacking faults lead to the peak position shifts, broadening and asymmetry of diffraction. XRD analysis and TEM observations revealed significant densities of stacking faults in LSP-treated 6061-T6 alloy. And mechanical properties of LSP-treated alloy were also determined to understand the hardening behavior with high concentration of structural defects.

Correlation of Lifetime Mapping of 4H-SiC Epilayers with Structural Defects Using Synchrotron X-Ray Topography

2016 ◽  
Vol 858 ◽  
pp. 297-300 ◽  
Author(s):  
O.Y. Goue ◽  
Yu Yang ◽  
J.Q. Guo ◽  
Balaji Raghothamachar ◽  
Michael Dudley ◽  
...  
Keyword(s):  
Grain Boundaries ◽  
Carrier Lifetime ◽  
Substrate Surface ◽  
Stacking Faults ◽  
High Density ◽  
Structural Defects ◽  
Middle Region ◽  
X Ray ◽  
Half Loop ◽  
Interfacial Dislocations

Lifetime maps for two 4H-SiC epi-wafers (samples 1 and 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the type and distribution of structural defects mapped by synchrotron X-ray topography (white beam and monochromatic). Sample 1 showed lower lifetime inside one of its higher doped facet regions and along its edges. The low lifetime in the facet region was associated with the presence of a high density of multi-layered Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). These stacking faults are likely double Shockley stacking faults (DSSFs) and probably nucleated from scratches present on the substrate surface and LAGBs present in that region, propagating during epilayer growth. In contrast, sample 2 showed a reduced carrier lifetime in the middle region associated with a network of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that are generated during epilayer growth. Along the edges of both samples, overlapping triangular defects, microcracks and BPD loops lowered lifetime.

Correlation between Strain and Excess Carrier Lifetime in a 3C-SiC Wafer

2012 ◽  
Vol 717-720 ◽  
pp. 305-308 ◽  
Author(s):  
Atsushi Yoshida ◽  
Masashi Kato ◽  
Masaya Ichimura
Keyword(s):  
Raman Spectroscopy ◽  
Optical Microscopy ◽  
Carrier Lifetime ◽  
Structural Defects ◽  
Free Standing ◽  
Excess Carrier ◽  
Carrier Lifetimes ◽  
Photoconductivity Decay ◽  
Sic Wafer

We obtained excess carrier lifetime maps by the microwave photoconductivity decay (µ-PCD) method in a free-standing n-type 3C-SiC wafer, and then we compared the lifetime maps with distributions of strains and defects observed by the optical microscopy and the Raman spectroscopy. We found that the excess carrier lifetimes are short in a strained region in 3C-SiC, which indicates that structural defects exist around a strained region.

SXRT Investigations on Electrically Stressed 4H-SiC PiN Diodes for 6.5 kV

2013 ◽  
Vol 740-742 ◽  
pp. 899-902 ◽  
Author(s):  
Birgit Kallinger ◽  
Patrick Berwian ◽  
Jochen Friedrich ◽  
Christian Hecht ◽  
Dethard Peters ◽  
...  
Keyword(s):  
Stress Test ◽  
Stacking Faults ◽  
Active Area ◽  
Structural Defects ◽  
Electrical Characteristics ◽  
Wafer Level ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Electrical Stress ◽  
Voltage Drift

4H-SiC PiN diodes for 6.5 kV were manufactured on both 4° and 8° off-cut substrates and subjected to an electrical stress test on wafer level and subsequent analysis of structural defects present in the active area of the diodes. For 8° off-cut diodes, the electrical characteristics with respect to leakage current and forward voltage drift are worse than the electrical characteristics of 4° off-cut diodes. Furthermore, a large number of stacking faults was found in 8° off-cut diodes, but little evidence for bipolar degradation was found in 4° off-cut diodes. Therefore, bipolar degradation was significantly reduced by avoiding BPDs in the active area of PiN diodes, i.e. by the use of 4° off-cut substrates. Furthermore, a strong correlation was found between the electrical screening test on wafer level and critical defects.

scholarly journals First Principles Investigation on Thermodynamic Properties and Stacking Fault Energy of Paramagnetic Nickel at High Temperatures

Metals ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 319
Author(s):  
Jing Zhang ◽  
Pavel A. Korzhavyi
Keyword(s):  
Mechanical Properties ◽  
Free Energy ◽  
Thermodynamic Properties ◽  
Temperature Dependence ◽  
First Principles ◽  
Elastic Moduli ◽  
Stacking Faults ◽  
Lattice Parameter ◽  
Stacking Fault ◽  
Stacking Fault Energies

Reliable data on the temperature dependence of thermodynamic properties of alloy phases are very useful for modeling the behavior of high-temperature materials such as nickel-based superalloys. Moreover, for predicting the mechanical properties of such alloys, additional information on the energy of lattice defects (e.g., stacking faults) at high temperatures is highly desirable, but difficult to obtain experimentally. In this study, we use first-principles calculations, in conjunction with a quasi-harmonic Debye model, to evaluate the Helmholtz free energy of paramagnetic nickel as a function of temperature and volume, taking into account the electronic, magnetic, and vibrational contributions. The thermodynamic properties of Ni, such as the equilibrium lattice parameter and elastic moduli, are derived from the free energy in the temperature range from 800 to 1600 K and compared with available experimental data. The derived temperature dependence of the lattice parameter is then used for calculating the energies of intrinsic and extrinsic stacking faults in paramagnetic Ni. The stacking fault energies have been evaluated according to three different methodologies, the axial-next-nearest-neighbor Ising (ANNNI) model, the tilted supercell approach, and the slab supercell approach. The results show that the elastic moduli and stacking fault energies of Ni decrease with increasing temperature. This “softening” effect of temperature on the mechanical properties of nickel is mainly due to thermal expansion, and partly due to magnetic free energy contribution.

Influence of in-Grown Stacking Faults on Electrical Characteristics of 4H-SiC Pin Diode with Long Carrier Lifetime

2013 ◽  
Vol 740-742 ◽  
pp. 903-906 ◽  
Author(s):  
Koji Nakayama ◽  
Atsushi Tanaka ◽  
Katsunori Asano ◽  
Tetsuya Miyazawa ◽  
Hidekazu Tsuchida
Keyword(s):  
Room Temperature ◽  
Carrier Lifetime ◽  
Stacking Faults ◽  
Pin Diode ◽  
Electrical Characteristics ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Voltage Drops ◽  
Implantation Process ◽  
Drift Layer

The electrical characteristics of 4H-SiC pin diodes with 8H-type in-grown stacking faults are investigated. The pin diodes have epilayers with low Z1/2center concentration formed by using the carbon implantation process. The forward voltage drops of the diode with 8H-type in-grown stacking faults are larger than those of the diode without a 8H-type in-grown stacking fault. At room temperature, the differential on-resistance of the pin diode with 8H-type in-grown stacking faults is larger than the value calculated from donor concentration in the drift layer by using the current transportation model of the unipolar device. Meanwhile, the differential on-resistances of the pin diode with 8H-type in-grown stacking faults decrease with an increase in temperature and become smaller than the calculated value at temperature of more than 200 °C.

Simulation of TEDREC Phenomena for 4H-SiC Pin Diode with p/n Type Drift Layer

2013 ◽  
Vol 740-742 ◽  
pp. 1107-1110 ◽  
Author(s):  
Koji Nakayama ◽  
Tetsuro Hemmi ◽  
Katsunori Asano
Keyword(s):  
Room Temperature ◽  
Stacking Faults ◽  
Stacking Fault ◽  
Pin Diode ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Voltage Drops ◽  
P Type ◽  
Room Temperature Increase ◽  
Drift Layer

Temperature dependence simulations of forward characteristics for 4H-SiC pin diodes with Shockley-type stacking faults are performed in order to investigate the mechanism of the TEDREC phenomena. The forward voltage drops of both n-type and p-type drift layers at room temperature increase as the length of the Shockley-type stacking fault increases. When the diodes are compared to each other at the same temperature, the differences between the forward voltage drops do not change significantly up to 150 oC, but the differences suddenly narrow in the range from 150 °C to 200 °C. The Shockley-type stacking fault prevents current from flowing at room temperature. The current, however, flows throughout the drifted diode when the temperature is raised.

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