scholarly journals Preparation and Characterization of Deposited Tetraethylorthosilicate-SiO2/SiC MIS Structure

2013 ◽  
Vol 740-742 ◽  
pp. 805-808 ◽  
Author(s):  
Mitsunori Hemmi ◽  
Takashi Sakai ◽  
Tomohiko Yamakami ◽  
Rinpei Hayashibe ◽  
Kiichi Kamimura
Keyword(s):  
Thermal Decomposition ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mis Structure ◽  
Interface Properties ◽  
Post Deposition Annealing ◽  
Direct Nitridation ◽  
Post Deposition

The SiO2 layer was deposited on the 4H-SiC Si face by the thermal decomposition of tetraethylorthosilicate(TEOS) in N2 atmosphere to from MIS diodes. The post deposition annealing was effective to improve the interface properties. The interface state density of the deposited SiO2/SiC MIS structure was estimated to be the order of 1011 cm-2eV-1 by Terman method. The direct nitridation of SiC surface prior to the deposition of the SiO2 layer was effective to reduce the interface state density.

Enhanced Channel Mobility in 4H-SiC MISFETs by Utilizing Deposited SiN/SiO2 Stack Gate Structures

2008 ◽  
Vol 600-603 ◽  
pp. 679-682 ◽  
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Post Deposition Annealing ◽  
Interface Quality ◽  
Channel Mobility ◽  
Capacitance Voltage ◽  
Mis Capacitors ◽  
Post Deposition ◽  
Time Lead

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

scholarly journals Effective mobility and interface-state density of La2O3 nMISFETs after post deposition annealing

2006 ◽  
Vol 3 (13) ◽  
pp. 316-321 ◽  
Author(s):  
Jin-Aun Ng ◽  
Nobuyuki Sugii ◽  
Kuniyuki Kakushima ◽  
Parhat Ahmet ◽  
Kazuo Tsutsui ◽  
...  
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Post Deposition Annealing ◽  
Effective Mobility ◽  
Post Deposition

Effect of Direct Nitridation of 4H-SiC Surface on MOS Interface States

2012 ◽  
Vol 717-720 ◽  
pp. 725-728 ◽  
Author(s):  
Takashi Sakai ◽  
Mitsunori Hemmi ◽  
Yusuke Murata ◽  
Tomohiko Yamakami ◽  
Rinpei Hayashibe ◽  
...  
Keyword(s):  
Thermal Decomposition ◽  
Deposition Process ◽  
Interface State ◽  
Nitride Layer ◽  
State Density ◽  
Interface State Density ◽  
Xps Analysis ◽  
Insulating Layer ◽  
Direct Nitridation ◽  
Mis Diode

A nitride layer was formed on a SiC surface by direct nitridation in pure N2 or in NH3 diluted with N2. The SiO2 layer was deposited by the thermal decomposition of tetraethylorthosilicate (TEOS) on the nitride layer to form an MIS diode. The XPS analysis showed that the nitride layer was oxidized during the deposition process of SiO2. The direct nitridation was effective to reduce the interface state density between the insulating layer and 4H-SiC

Characterization of POCl3-Annealed 4H-Sic Mosfets by Charge Pumping Technique

2013 ◽  
Vol 740-742 ◽  
pp. 541-544 ◽  
Author(s):  
Ai Osawa ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Lower Half ◽  
Interface Properties ◽  
Charge Pumping

4H-SiC MOSFETs were characterized using charge pumping (CP) technique to monitor interface state density (Dit) not only in the upper half of the bandgap (Eg) but also in the lower half of Eg. Comparison between POCl3- and NO-annealed MOSFETs was made using CP technique to reveal the different interface properties. The CP measurements of MOSFETs revealed that POCl3 annealing can reduce Dit near Ec, whereas it increases donor-like Dit in the lower half of Eg.

scholarly journals Preparation and Characterization of Nitridation Layer on 4H SiC (0001) Surface by Direct Plasma Nitridation

2014 ◽  
Vol 778-780 ◽  
pp. 631-634 ◽  
Author(s):  
Yoshiyuki Akahane ◽  
Takuo Kano ◽  
Kyosuke Kimura ◽  
Hiroki Komatsu ◽  
Yukimune Watanabe ◽  
...  
Keyword(s):  
Interface State ◽  
Nitride Layer ◽  
State Density ◽  
Interface State Density ◽  
Process Temperature ◽  
Pure Nitrogen ◽  
Interface Property ◽  
Plasma Nitridation

A nitride layer was formed on a SiC surface by plasma nitridation using pure nitrogen as the reaction gas at the temperature from 800°C to 1400°C. The surface was characterized by XPS. The XPS measurement showed that an oxinitride layer was formed on the SiC surface by the plasma nitridation. The high process temperature seemed to be effective to activate the niridation reaction. A SiO2film was deposited on the nitridation layer to form SiO2/nitride/SiC structure. The interface state density of the SiO2/nitride/SiC structure was lower than that of the SiO2/SiC structure. This suggested that the nitridation was effective to improve the interface property.

Characterization of Wet Chemical Atomic Layer Etching of InGaAs

2021 ◽  
Vol 314 ◽  
pp. 95-98
Author(s):  
Tomoki Hirano ◽  
Kenya Nishio ◽  
Takashi Fukatani ◽  
Suguru Saito ◽  
Yoshiya Hagimoto ◽  
...  
Keyword(s):  
Surface Condition ◽  
Atomic Layer ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Etching Process ◽  
Wet Chemical ◽  
Oxide Removal ◽  
Atomic Layer Etching

In this work, we characterized the wet chemical atomic layer etching of an InGaAs surface by using various surface analysis methods. For this etching process, H2O2 was used to create a self-limiting oxide layer. Oxide removal was studied for both HCl and NH4OH solutions. Less In oxide tended to remain after the HCl treatment than after the NH4OH treatment, so the combination of H2O2 and HCl is suitable for wet chemical atomic layer etching. In addition, we found that repetition of this etching process does not impact on the oxide amount, surface roughness, and interface state density. Thus, nanoscale etching of InGaAs with no impact on the surface condition is possible with this method.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

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