scholarly journals Impact of Hot Carrier Degradation and Positive Bias Temperature Stress on Lateral 4H-SiC nMOSFETs

2014 ◽  
Vol 778-780 ◽  
pp. 959-962 ◽  
Author(s):  
Gregor Pobegen ◽  
Thomas Aichinger ◽  
Alberto Salinaro ◽  
Tibor Grasser
Keyword(s):  
Temperature Stress ◽  
Interface Traps ◽  
Positive Bias ◽  
Limited Information ◽  
Degradation Mechanisms ◽  
Hot Carrier ◽  
Bias Temperature Stress ◽  
Silicon Based ◽  
Induced Defects ◽  
The Impact

We study the impact of positive bias temperature stress and hot carrier stress on lateral 4H-SiC nMOSFETs. These degradation mechanisms are prominent in silicon based devices where both create oxide as well as interface traps. For SiC MOSFETs only limited information regarding these mechanisms is available. We transfer the charge pumping technique, known from Si MOSFETs, reliably to SiC MOSFETs to learn about the nature of the stress induced defects.

Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress

2016 ◽  
Vol 858 ◽  
pp. 481-484 ◽  
Author(s):  
Gerald Rescher ◽  
Gregor Pobegen ◽  
Tibor Grasser
Keyword(s):  
Temperature Stress ◽  
Threshold Voltage ◽  
Physical Property ◽  
Oxide Thickness ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Power Mosfets ◽  
Fundamental Physical Property ◽  
Bias Temperature Stress ◽  
Silicon Based

We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC-SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.

Impact of Nitric Oxide Post Oxidation Anneal on the Bias Temperature Instability and the On-Resistance of 4H-SiC nMOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 709-712 ◽  
Author(s):  
Gerald Rescher ◽  
Gregor Pobegen ◽  
Thomas Aichinger
Keyword(s):  
Nitric Oxide ◽  
Electric Field ◽  
Temperature Stress ◽  
Threshold Voltage ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Bias Temperature Instability ◽  
Bias Temperature Stress ◽  
The Impact ◽  
Stress Voltage

We study the impact of different nitric oxide (NO) post oxidation annealing (POA) procedures on the on resistance Ron of n-channel MOSFETs and on the threshold voltage shift ∆Vth following positive bias temperature stress (PBTS). All samples were annealed in an NO containing atmosphere at various temperatures and times. A positive stress voltage of 30 V was chosen which corresponds to an electric field of about 4.3 MV/cm. The NO POA causes a decrease in overall ∆Vth for longer NO POA times and higher NO POA temperatures. As opposed to the change in ∆Vth, the device Ron increases with NO POA temperature and time.

scholarly journals Insight Into Electron Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging

2016 ◽  
Vol 63 (9) ◽  
pp. 3642-3648 ◽  
Author(s):  
Meng Duan ◽  
Jian Fu Zhang ◽  
Zhigang Ji ◽  
Wei Dong Zhang ◽  
David Vigar ◽  
...  
Keyword(s):  
Energy Distribution ◽  
Temperature Stress ◽  
Positive Bias ◽  
Electron Traps ◽  
Hot Carrier ◽  
Bias Temperature Stress ◽  
Insight Into

Hydrogen as a Cause of Abnormal Subchannel Formation Under Positive Bias Temperature Stress in a-InGaZnO Thin-Film Transistors

2019 ◽  
Vol 66 (7) ◽  
pp. 2954-2959
Author(s):  
Yu-Chieh Chien ◽  
Yi-Chieh Yang ◽  
Yu-Ching Tsao ◽  
Hsiao-Cheng Chiang ◽  
Mao-Chou Tai ◽  
...  
Keyword(s):  
Thin Film ◽  
Temperature Stress ◽  
Thin Film Transistors ◽  
Positive Bias ◽  
Bias Temperature Stress

Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

1989 ◽  
Vol 36 (9) ◽  
pp. 1732-1739 ◽  
Author(s):  
Y. Hiruta ◽  
H. Iwai ◽  
F. Matsuoka ◽  
K. Hama ◽  
K. Maeguchi ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Interface State ◽  
Positive Bias ◽  
Mos Structure ◽  
State Generation ◽  
Bias Temperature Stress

Drain Bias Effect on the Interface Traps of pMOSFETs under Negative Bias Temperature Stress

2019 ◽  
Vol 18 (1) ◽  
pp. 219-223
Author(s):  
Junyan Pan ◽  
Jiaqi Yang ◽  
Ying Qiao ◽  
X.Y. Liu ◽  
Ruqi Han ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Negative Bias ◽  
Interface Traps ◽  
Bias Effect ◽  
Drain Bias ◽  
Bias Temperature Stress

Impact of Hydrogen Implantation on Helium Implantation Induced Defects

2005 ◽  
Vol 108-109 ◽  
pp. 309-314 ◽  
Author(s):  
G. Gaudin ◽  
Frédéric Cayrel ◽  
Corrado Bongiorno ◽  
Robert Jérisian ◽  
Vito Raineri ◽  
...  
Keyword(s):  
Cavity Growth ◽  
High Dose ◽  
Defect Band ◽  
Hydrogen Addition ◽  
Recent Developments ◽  
Hydrogen Implantation ◽  
Helium Implantation ◽  
Silicon Based ◽  
Induced Defects ◽  
The Impact

Silicon-based power device performances are largely affected by metal contamination occurring during device manufacturing. Among the usual gettering techniques, recent developments were done on high dose helium implantation. Even though the gettering efficiency of this technique has been demonstrated in device application, the required doses are still extremely high for an industrial application. Recently, it has been shown that the use of H/He co-implantation limits the total requested doses [1]. In this paper, co-implantation of H/He, which has been already used to reduce the dose in the smart-cut® process is explored. The goal of this work is to decrease efficiently the implanted dose maintaining an efficient metallic gettering without degrading the Si surface. The impact of H implantation on He implantation induced defects is carefully studied. The TEM observations have evidenced that hydrogen addition drastically modified the defect band structure and promotes the cavity growth.. Additionally, we demonstrate that an efficient gettering can be obtained.

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