In-Plane Longitudinal Cutting in Single-Crystal Silicon Wafer Surface Micromachining

2017 ◽  
Vol 261 ◽  
pp. 93-100
Author(s):  
Ronald Allan S. de los Reyes
Keyword(s):  
Silicon Crystal ◽  
Abrasive Particle ◽  
Silicon Wafers ◽  
Wafer Surface ◽  
Surface Layers ◽  
Cutting Mechanism ◽  
Spherical Cap ◽  
Appreciable Change ◽  
Polymorphic Transitions ◽  
Longitudinal Cutting

The current concept of grinding or abrasive machining involves the formation and removal of segmented strips of material termed chips from the surface of the solid. A novel cutting mechanism is hereby presented in this research study that suggests that the generation of chips from the surface does not occur but only a shearing process that splits material creating added surface features and textures in the silicon surface. This arises from the unique set of factors of abrasive grit size, thrust force, polishing speed, and polishing time that lead to phase transformations in the surface layers of the silicon wafers. Statistical analysis of the factor effects yielded results that show the surface roughness values, Ra and Rz, increasing without any appreciable change in the thickness of the silicon wafers. This can be attributed to the proposed cutting mechanism indicating that only in-plane surface shearing occurred due to the change of the silicon crystal structure from exhibiting brittle behavior to that of ductile mode of deformation. Moreover, experimental quantities of the specific energy for surface machining of silicon was calculated with an overall mean of 50.5 GPa. This is about 33% less than the currently accepted value and can be considered further evidence that polymorphic transitions to a softer material occurred rendering the surface layers more susceptible to longitudinal cutting deformation and fracture. A model based on the inverted spherical cap or spherical bottom geometry for the individual abrasive particle is also proposed, verified by a finite element method analysis simulation, that can mathematically describe this particular micromachining process.

Analysis of Handling Stresses in Thin Solar Silicon Wafers Generated by a Rigid Vacuum Gripper

2015 ◽  
Vol 138 (3) ◽  
Author(s):  
Hao Wu ◽  
Shreyes N. Melkote
Keyword(s):  
Stress Distribution ◽  
Dominant Role ◽  
High Stress ◽  
Surface Profile ◽  
Silicon Wafers ◽  
Wafer Surface ◽  
Initial Surface ◽  
Fe Modeling ◽  
Solar Silicon ◽  
Surface Profiles

Breakage of thin solar silicon wafers during handling and transport depends on the stresses imposed on the wafer by the handling/transport device. In this paper, the stresses generated in solar silicon wafers by a rigid vacuum gripper are analyzed via a combination of experiments and numerical modeling. Specifically, stresses produced in monocrystalline (Cz) and multicrystalline (Cast) silicon wafers of different thicknesses when handled by a vacuum gripper are analyzed using the finite element (FE) method. With the measured surface profiles of the wafer and the gripper as input, the handling process is simulated using FE modeling and the stress distribution obtained. The FE modeling results are validated by experimental data of wafer surface profile during handling. The results show that while the vacuum level does not have significant impact on the stress distribution, the initial surface profiles of the thin wafer and gripper play a dominant role in producing regions of high stress in the wafer.

Wafer bonding of silicon wafers covered with various surface layers

2000 ◽  
Vol 86 (1-2) ◽  
pp. 91-95 ◽  
Author(s):  
M Wiegand ◽  
M Reiche ◽  
U Gösele ◽  
K Gutjahr ◽  
D Stolze ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Silicon Wafers ◽  
Surface Layers

scholarly journals Simulation of silicon wafers heating during rapid thermal processing using “UBTO 1801” unit

Doklady BGUIR ◽  
2020 ◽  
Vol 18 (7) ◽  
pp. 79-86
Author(s):  
J. A. Solovjov ◽  
V. A. Pilipenko ◽  
V. P. Yakovlev
Keyword(s):  
Mathematical Model ◽  
Silicon Wafer ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Light Flux ◽  
Silicon Wafers ◽  
Wafer Surface ◽  
Constant Density ◽  
Wafer Temperature

The present work is devoted to determination of the dependence of the heating temperature of the silicon wafer on the lamps power and the heating time during rapid thermal processing using “UBTO 1801” unit by irradiating the wafer backside with an incoherent flow of constant density light. As a result, a mathematical model of silicon wafer temperature variation was developed on the basis of the equation of nonstationary thermal conductivity and known temperature dependencies of the thermophysical properties of silicon and the emissivity of aluminum and silver applied to the planar surface of the silicon wafer. For experimental determination of the numerical parameters of the mathematical model, silicon wafers were heated with light single pulse of constant power to the temperature of one of three phase transitions such as aluminum-silicon eutectic formation, aluminum melting and silver melting. The time of phase transition formation on the wafer surface during rapid thermal processing was fixed by pyrometric method. In accordance with the developed mathematical model, we determined the conversion coefficient of the lamps electric power to the light flux power density with the numerical value of 5.16∙10-3 cm-2 . Increasing the lamps power from 690 to 2740 W leads to an increase in the silicon wafer temperature during rapid thermal processing from 550°to 930°K, respectively. With that, the wafer temperature prediction error in compliance with developed mathematical model makes less than 2.3 %. The work results can be used when developing new procedures of rapid thermal processing for silicon wafers.

scholarly journals Study on abrasive particle impact modeling and cutting mechanism

2021 ◽  
Author(s):  
Mingfei Mu ◽  
Long Feng ◽  
Qiang Zhang ◽  
Wanshun Zang ◽  
Haixia Wang
Keyword(s):  
Abrasive Particle ◽  
Particle Impact ◽  
Cutting Mechanism

Dynamics of the Formation of the Subambient Pressure Distribution During Chemical-Mechanical Polishing

2007 ◽  
Author(s):  
A. Osorno ◽  
S. Tereshko ◽  
I. Yoon ◽  
S. Danyluk
Keyword(s):  
Integrated Circuits ◽  
Pressure Distribution ◽  
Chemical Mechanical Polishing ◽  
Rotational Speed ◽  
Silicon Wafers ◽  
Mechanical Polishing ◽  
Wafer Surface ◽  
Abrasive Particles ◽  
Pressure Distributions ◽  
Time Period

Chemical-Mechanical Polishing is used to polish silicon wafers in the manufacturing of integrated circuits. Wafers are pressed, electronics side down, onto a rotating pad that is flooded with a slurry containing abrasive particles. The slurry is entrained in the interface and the abrasive particles slide against the silicon and polish it. Our previous work has shown that subambient pressures develop at the silicon/pad interface and we have measured this pressure and its distribution over the wafer surface (1). However, our experiments have been limited to those conditions where the pad rotates and the wafer slides on the pad but the wafer itself does not rotate. Our experiments showed a skewed pressure distribution. This paper describes experiments and pressure distribution measurements where the wafer, as well as the pad/platen is rotated (2). Specifically-designed wireless electronic transmitters and receivers were built and used to measure the interfacial pressures at the silicon/pad interface. Subambient stress maps and temperatures have been measured and Figure 1 shows an example of a skewed pressure distribution when the silicon is not rotated and Figure 2 shows the pressure distribution for the same wafer while it is rotating. The subambient pressures develop over a 2 second time period from when the rotation started. The pressure distributions are symmetric in spite of the lean and tilt of the wafers. The rotational speed and other variables have a big influence on the polishing rate and this will be discussed in the talk.

Modeling the Tensile Strength and Crack Length of Wire-Sawn Silicon Wafers

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
Claudia Funke ◽  
Susann Wolf ◽  
Dietrich Stoyan
Keyword(s):  
Stress Distribution ◽  
Crack Length ◽  
Fracture Stress ◽  
Quantitative Description ◽  
Silicon Wafers ◽  
Wafer Surface ◽  
Truncation Parameter ◽  
Solar Silicon ◽  
Intensity Functions ◽  
The Impact

Solar silicon wafers are mainly produced through multiwire-sawing. This sawing implies microcracks on the wafer surface, which are responsible for brittle fracture. In order to reduce the sawing-induced cracks, the wafers are damage etched after sawing. This paper develops a model for the impact of crack length manipulation on fracture stress distribution. It investigates the effect of damage-etching on the mechanical properties of solar silicon wafers. The main idea is to transform the fracture stress distribution into a crack length intensity function and to model the effect of etching in terms of crack lengths. The fracture stress distribution is determined statistically by fracture tests of wire-sawn and sawn and etched wafers. The Griffith criterion then enables the transition to crack lengths and crack length intensity functions. Two numerical parameters, called truncation parameter and scaling parameter, determine this relationship and enable a quantitative description of the effect of etching. They turn out to be dependent on etchant and geometry of load and thus tested crack population.

Modeling Stresses of Contacts in Wire Saw Slicing of Polycrystalline and Crystalline Ingots: Application to Silicon Wafer Production

1998 ◽  
Vol 120 (2) ◽  
pp. 123-128 ◽  
Author(s):  
J. Li ◽  
I. Kao ◽  
V. Prasad
Keyword(s):  
Maximum Shear Stress ◽  
Silicon Crystal ◽  
Silicon Wafers ◽  
Cutting Process ◽  
Abrasive Particles ◽  
Silicon Ingot ◽  
Wire Saw ◽  
Dimensionless Stress ◽  
Tangential Forces ◽  
The Wire

Wire saw slicing is a cost effective technology with high surface quality for slicing large diameter silicon wafers. Though wire saws have been deployed to cut polycrystalline and single crystal silicon ingot since the early 1990s, very little is known about the fundamental cutting process. We investigate this manufacturing process and propose a contact stress model of wire saw slicing that illustrates the interactions among the wire, ingot, and abrasives (e.g., SiC) carried by the slurry. Stresses created by wire saw slicing silicon wafers are analyzed in this paper. During the cutting process, the wire moves at high speed (5–15 m/s) with respect to the silicon ingot. The abrasives in the slurry are lose third-body particles caught between the wire and ingot at the contact surface. The forces applied by the wire carry the abrasive particles and cause them to roll on the surface and at the same time to be constrained to indent the surface. Such rolling-indenting interactions result in the formation of isolated chips and surface cracks. The cracks and discontinuity on the surface also cause high stress concentration. As a result, the material is cut and removed. The stress fields of a single circular cone of the abrasive particle indenting on silicon crystal with normal and tangential forces can be calculated and analyzed from the modeling equations and boundary conditions. The stresses are expressed with dimensionless stress measures, as functions of normalized geometric parameters. The results show that the maximum normal stress occurs at the indentation point, while the maximum shear stress (σzx) occurs below the surface of contact, as expected. Such subsurface shear facilitates the peeling effects of the silicon cracks. Both the normal and tangential forces applied at the contacts are incorporated in the model. The model is very effective in explaining and predicting the behaviors and distributions of stresses during the cutting process, and can be used to determine the optimal geometry of the abrasive particles in the rolling-indenting process.

An Economic Study on Chemical Mechanical Polishing of Silicon Wafers

2009 ◽  
Author(s):  
Emmanuel A. Baisie ◽  
Man Yang ◽  
Ravindra Kaware ◽  
Maria Hooker ◽  
Z. C. Li ◽  
...  
Keyword(s):  
Chemical Mechanical Polishing ◽  
Cost Model ◽  
Labor Cost ◽  
Silicon Wafers ◽  
Mechanical Polishing ◽  
Wafer Surface ◽  
Variable Cost ◽  
Fixed Cost ◽  
Economic Study ◽  
Total Cost

Chemical mechanical polishing (CMP) is used to remove irregularities on the silicon wafer surface. The importance of CMP is the achievement of both local and global planarity of wafer surface. This paper presents an economic study on CMP of silicon wafers. A cost model is developed to predict the total cost for CMP of silicon wafers. An input-output model is developed to analyze parameters relevant to the fixed cost and variable cost. The labor cost is investigated through a flow chart of the labor operation. Based on the cost model, a hypothetical case study is conducted to show the model’s capability of performing sensitivity analysis and identifying critical factors for the total cost for strategic management purposes.

scholarly journals Study of the influence of ozone-air mixture supply conditions on the process of the photoresist removal from the silicon wafer surface

Doklady BGUIR ◽  
2020 ◽  
Vol 18 (6) ◽  
pp. 57-65
Author(s):  
O. I. Tsikhan ◽  
S. I. Madveika ◽  
S. V. Bordusau ◽  
A. L. Barakhoev ◽  
P. V. Kamlach
Keyword(s):  
Silicon Wafer ◽  
Gas Flow ◽  
Removal Rate ◽  
Temperature Drop ◽  
Complete Removal ◽  
Silicon Wafers ◽  
Wafer Surface ◽  
Mixture Flow ◽  
Heated Sample ◽  
Temperature Regimes

The study is devoted to the research of the dependence of the processing results of photoresistive films on the silicon wafers surface in an ozone environment on the conditions and parameters of the process. The high oxidizing potential of ozone justifies the possibility of its use for removing organic films under atmospheric pressure. The experiments were carried out using the developed research bench, in which the mode and method of heating, as well as the method of supplying gas to the surface of the photoresist, were varied. Silicon wafers with a formed 1,35-μm thick masking photoresist film were used as experimental samples. It was found expedient that uniform heating of the plate over its entire surface can be achieved using a ceramic IR heater. When the ozone-air mixture was introduced into the center of the heated sample, the presence of the removed photoresist residues was observed, which was associated with a temperature drop in its surface area. To solve this problem, the computer models of the temperature regimes of the reaction volume elements were calculated. They showed that the scattering of the working gas flow over the surface of the silicon wafer would significantly increase the efficiency of photoresist removal, and with a good selection of the treatment regime it would ensure complete removal of the photoresist. The data obtained were experimentally confirmed by using an ozone-air mixture flow separator. Experiments were carried out to study the effect of the distance from the wafer surface to the working gas inlet on the photoresist removal rate. They showed that a decrease in the distance reduces the ozone loss due to thermal decomposition and, consequently, increases the material removal rate.

Fracture Analysis and Distribution of Surface Cracks in Multicrystalline Silicon Wafers

2013 ◽  
Vol 136 (2) ◽  
Author(s):  
S. Saffar ◽  
S. Gouttebroze ◽  
Z. L. Zhang
Keyword(s):  
Failure Probability ◽  
Surface Crack ◽  
Silicon Wafers ◽  
Multicrystalline Silicon ◽  
Wafer Surface ◽  
Surface Cracks ◽  
Property Variation ◽  
Micro Cracks ◽  
Solar Silicon ◽  
Sawing Process

Solar silicon wafers are mainly produced through multiwire sawing. The sawing process induces micro cracks on the wafer surface, which are responsible for brittle fracture. Hence, it is important to scrutinize the crack geometries most commonly generated in silicon wafer sawing or handling process and link the surface crack to the fracture of wafers. The fracture of a large number of multicrystalline silicon wafers has been investigated by means of 4-point bending and twisting tests and a failure probability function is presented. By neglecting the material property variation and assuming that one surface crack is dominating the wafer breakage, 3D finite element models with various crack sizes (depth, length, and orientation) have been analyzed to identify the distribution of surface crack geometries by fitting the failure probability from the experiments. With respect to the 63% probability, the existing surface cracks in the wafers studied appear to have depth and length ratios less than 0.042 and 0.19, respectively. Furthermore, it has been shown that the surface cracks with depth in the range from 10 to 20 μm, length up to 10 mm and angles in the range of 30 deg–60 deg, can be considered as the most common crack geometries in wafers we tested. Finally, it has been found that the mechanical strength of the wafers tested parallel to the sawing direction is approximately 15 MPa smaller than those tested perpendicular to the sawing direction.

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