Wafer-level packaging of RF MEMS devices offers an attractive option to reduce packaging cost significantly and ensures hermetic encapsulation of devices. Low-temperature cofired ceramic (LTCC) cap wafers are particularly favorable because they can be pre-patterned with through-wafer vias for integrated electrical contacts and high-density packaging, at a much lower cost than silicon wafers with similar features. However, thermal expansion mismatch between ceramic and silicon wafers at high bonding temperatures induces thermal stresses at the interface, resulting in wafer curvature. For example, a 150 mm silicon wafer 675 μm thick with a ceramic cap wafer 500 μm thick has been measured to exhibit out-of-flatness displacement as severe as of 1.7 mm at the center. While the curvature can be reduced significantly using low-thermal-expansion ceramic, such materials are non-standard and require custom formulation. Furthermore, as the wafer diameter is increased, thermal expansion mismatch becomes more problematic. Therefore, it is desirable to address the problem using a geometrical approach in addition to optimizing the ceramic for wafer bonding applications. The present study applies finite element analysis (FEA) to examine the potential for reducing such curvature by introducing slots in the ceramic cap wafer. Two-level factorial design simulations involving five parameters were conducted to investigate the effect of slot parameters on wafer curvature, using 2-D plane strain simulation of wafer cooling from 300 °C to 25 °C. The five parameters investigated were cap wafer thickness, slot width, slot depth, slot separation, and slot orientation. The nonlinear temperature dependence of thermal expansion was also examined based on test data for the ceramic wafers. Furthermore, a 3-D finite element simulation was conducted to compare the 2-D results to overall impact on wafer distortion. FEA results were compared with experimental curvature measurements on sample wafers measured by coordinate measuring machining (CMM). Simulated results suggest that introduction of slots shows reduction in wafer curvature, and the displacement can be reduced by as much as 25% based on the geometric parameter values for slots in the cap wafer.
A new technique for observing the amorphous to crystalline transformation in thin surface layers on silicon wafers
