Toward the Surface Preparation of InGaAs for the Future CMOS Integration

2018 ◽  
Vol 282 ◽  
pp. 39-42 ◽  
Author(s):  
Sang Woo Lim
Keyword(s):  
Lattice Mismatch ◽  
Surface Reactions ◽  
Surface Preparation ◽  
Surface Oxidation ◽  
Compound Semiconductors ◽  
Compound Semiconductor ◽  
Wet Etching ◽  
Material Loss ◽  
High K ◽  
Made In

The integration of III-V and Ge materials on Si surface causes many issues with complexity such as lattice mismatch with silicon. In particular, the surface preparation and passivation of InGaAs is very challenging, because the formation of InGaAs/high-K interface is important, but not well understood. For the systematical study of InGaAs surface during wet processes, the effect of various wet etching processes on the surfaces of binary III-V compound semiconductors (GaAs, InAs, GaSb and InSb) was studied from the viewpoints of surface oxidation, material loss (dissolution), and passivation. Based on that, further effort to understand the surface reactions on ternary InGaAs compound semiconductor was made. In addition, process sequential effect on the InGaAs surface was investigated.

In-Situ Study of NiO Growth on Textured Nickel Tape Using Environmental Scanning Electron Microscope (ESEM) and Hot Stage

2001 ◽  
Vol 7 (S2) ◽  
pp. 1276-1277
Author(s):  
Y. Akin ◽  
R.E. Goddard ◽  
W. Sigmund ◽  
Y.S. Hascicek
Keyword(s):  
Buffer Layer ◽  
Lattice Mismatch ◽  
Sol Gel ◽  
Surface Oxidation ◽  
Dip Coating ◽  
Buffer Layers ◽  
Superconducting Film ◽  
Environmental Scanning ◽  
Cold Rolling And Annealing

Deposition of highly textured ReBa2Cu3O7−δ (RBCO) films on metallic substrates requires a buffer layer to prevent chemical reactions, reduce lattice mismatch between metallic substrate and superconducting film layer, and to prevent diffusion of metal atoms into the superconductor film. Nickel tapes are bi-axially textured by cold rolling and annealing at appropriate temperature (RABiTS) for epitaxial growth of YBa2Cu3O7−δ (YBCO) films. As buffer layers, several oxide thin films and then YBCO were coated on bi-axially textured nickel tapes by dip coating sol-gel process. Biaxially oriented NiO on the cube-textured nickel tape by a process named Surface-Oxidation- Epitaxy (SEO) has been introduced as an alternative buffer layer. in this work we have studied in situ growth of nickel oxide by ESEM and hot stage.Representative cold rolled nickel tape (99.999%) was annealed in an electric furnace under 4% hydrogen-96% argon gas mixture at 1050°C to get bi-axially textured nickel tape.

scholarly journals Sodium Movements in the Human Red Blood Cell

1970 ◽  
Vol 56 (3) ◽  
pp. 322-341 ◽  
Author(s):  
John R. Sachs
Keyword(s):  
Blood Cell ◽  
Rate Constant ◽  
Transport Mechanism ◽  
Extracellular Potassium ◽  
Sodium Influx ◽  
Influx Rate ◽  
High K ◽  
Inner Surface ◽  
Pump Mechanism ◽  
Made In

Measurements were made of the sodium outflux rate constant, okNa, and sodium influx rate constant, ikNa, at varying concentrations of extracellular (Nao) and intracellular (Nac) sodium. okNa increases with increasing [Nao] in the presence of extracellular potassium (Ko) and in solutions containing ouabain. In K-free solutions which do not contain ouabain, okNa falls as [Nao] rises from 0 to 6 mM; above 6 mM, okNa increases with increasing [Nao]. Part of the Na outflux which occurs in solutions free of Na and K disappears when the cells are starved or when the measurements are made in solutions containing ouabain. As [Nao] increases from 0 to 6 mM, ikNa decreases, suggesting that sites involved in the sodium influx are becoming saturated. As [Nac] increases, okNa at first increases and then decreases; this relation between okNa and [Nac] is found when the measurements are made in high Na, high K solutions; high Na, K-free solutions; and in (Na + K)-free solutions. The relation may be the consequence of the requirement that more than one Na ion must react with the transport mechanism at the inner surface of the membrane before transport occurs. Further evidence has been obtained that the ouabain-inhibited Na outflux and Na influx in K-free solutions represent an exchange of Nac for Nao via the Na-K pump mechanism.

Enhanced Surface Preparation Techniques for the Si/High-k Interface

2005 ◽  
Vol 103-104 ◽  
pp. 11-14 ◽  
Author(s):  
Joel Barnett ◽  
Chadwin D. Young ◽  
Naim Moumen ◽  
Gennadi Bersuker ◽  
Jeff J. Peterson ◽  
...  
Keyword(s):  
Surface Preparation ◽  
High K ◽  
Enhanced Surface ◽  
Preparation Techniques

Surface Preparation Techniques for High-k Deposition on Ge Substrates

2005 ◽  
pp. 31-36
Author(s):  
Sven Van Elshocht ◽  
A. Delabie ◽  
B. Brijs ◽  
Matty Caymax ◽  
Thierry Conard ◽  
...  
Keyword(s):  
Surface Preparation ◽  
High K ◽  
Preparation Techniques

Selective Wet Etching of High-k Gate Dielectrics

2003 ◽  
Vol 92 ◽  
pp. 129-131 ◽  
Author(s):  
Kurt K. Christenson ◽  
Brent Schwab ◽  
Thomas J. Wagener ◽  
Bruce Rosengren ◽  
Deborah J. Riley ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Wet Etching ◽  
High K

Physical characterization of HfO2deposited on Ge substrates by MOCVD.

2004 ◽  
Vol 811 ◽  
Author(s):  
S. Van Elshocht ◽  
B. Brijs ◽  
M. Caymax ◽  
T. Conard ◽  
S. De Gendt ◽  
...  
Keyword(s):  
Physical Properties ◽  
Gate Dielectric ◽  
Substrate Material ◽  
Silicon Substrates ◽  
Enabling Technology ◽  
The Past ◽  
High K ◽  
Alternative Approach ◽  
Made In

ABSTRACTGermanium is because of its intrinsically higher mobility than Si, currently under consideration as an alternative approach to improve transistor performance. Germanium oxide, however, is thermodynamically unstable, preventing formation of the gate dielectric by simple oxidation. At present, high-k dielectrics might be considered as an enabling technology as much progress has been made in the deposition of thin high-quality layers.In this paper, we study the growth and physical properties of HfO2 deposited on Ge by MOCVD, using TDEAH and O2 as precursors, and compare the results to similar layers deposited on silicon substrates. Our results show that the physical properties of MOCVD-deposited HfO2 layers on Ge are very similar to what we have observed in the past for Si. Unfortunately, some of the negative aspects observed for Si, such as diffusion of substrate material in the high-k layer, a low density for thinner layers, or a rough top surface, are also observed for the case of Ge. However, careful surface pretreatments such as NH3 annealing the Ge substrate prior to deposition, can greatly improve the physical properties. An important observation is the very thin interfacial layer between HfO2 and Ge substrate, allowing a more aggressive scaling for Ge.

Surface Preparation of Poly-Si Using Dry Cleaning for Minimizing Interfacial Resistance

2012 ◽  
Vol 195 ◽  
pp. 71-74
Author(s):  
Choong Kee Seong ◽  
Tae Soo Lim ◽  
Jeong Gil Lee ◽  
Jin I Lee ◽  
Ki Jong Park ◽  
...  
Keyword(s):  
Boron Oxide ◽  
High Speed ◽  
Silicon Oxide ◽  
Surface Preparation ◽  
Surface Oxidation ◽  
Interfacial Resistance ◽  
Metal Gate ◽  
Dry Cleaning ◽  
Low Resistivity ◽  
Integration Density

As the integration density of memory increases, a low resistivity gate electrode is essential to meet the current needs of high speed operation. It has been known that one of major limitation of low resistivity gate is dopant penetration between poly-si and metal gate. Those dopants are penetrated and segregated on the surface of poly-si when annealed, which increases interfacial resistance and causes detrimental performance on the devices. Surface oxidation, level of boron oxide or silicon oxide on the poly-si surface is also getting higher after annealing. Therefore, it is necessary to remove those dopants oxidized layers on the surface of the activated poly-si in order to obtain minimal increases of interfacial resistance.

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