Silicon Corrosion during Selective Silicon Nitride Etch with Hot Diluted Hydrofluoric Acid

2021 ◽  
Vol 314 ◽  
pp. 107-112
Author(s):  
Philippe Garnier ◽  
Thomas Massin ◽  
Corentin Chatelet ◽  
Emmanuel Oghdayan ◽  
Jeffrey Lauerhaas ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Hydrofluoric Acid ◽  
Orthophosphoric Acid ◽  
Deionized Water ◽  
Silicon Surfaces ◽  
Shallow Trench Isolation ◽  
Trench Isolation

Silicon nitride is commonly etched by hot orthophosphoric acid. Hot diluted hydrofluoric acid is hereby used as an alternative. Nonetheless, in presence of silicon surfaces, some corrosion has been evidenced, degrading significantly active areas during the STI (Shallow Trench isolation) integration. Oxygen in hot deionized water or hot HF generates this corrosion and selecting a relevant chemical oxide before dispensing hot diluted HF is key in solving the concern.

Colloidal Silica based High Selectivity Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Slurry

2005 ◽  
Vol 867 ◽  
Author(s):  
Kyoung-Ho Bu ◽  
Brij M. Moudgil
Keyword(s):  
Silicon Nitride ◽  
Chemical Mechanical Polishing ◽  
Colloidal Silica ◽  
Sodium Dodecyl ◽  
Mechanical Polishing ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Pattern Size ◽  
Trench Isolation ◽  
Silica Slurry

AbstractAmong various properties of chemical mechanical polishing (CMP) slurry, selectivity plays a key role in global planarization of high density and small pattern size shallow trench isolation (STI) process. Lack of adequate selectivity can lead to defects such as dishing and erosion. To improve the selectivity of STI CMP process, CMP characteristics of silica and silicon nitride wafer were investigated using colloidal silica slurry as a function of slurry pH. Sodium dodecyl sulfate (SDS), an anionic surfactant, was added to increase the selectivity of the slurry. As a result, selectivity increased from 3 to 25. It was concluded that selective passivation layer formed on silicon nitride wafer surface at acidic slurry pH range was responsible for the observed selectivity increase. Adsorption characteristics of SDS on silica and silicon nitride were measured as a function of slurry pH and concentration of SDS. As indicated by zeta potential behavior under acidic pH conditions, SDS adsorption on silicon nitride was significantly higher han silica due to the electrostatic forces. Significantly higher SDS coating on silicone nitride seems to have resulted in lubrication layer leading to increased polishing selectivity.

Electrical AFM Measurements for Evaluation of Nitride Erosion in Shallow Trench Isolation Chemical Mechanical Planarization

2004 ◽  
Vol 838 ◽  
Author(s):  
Yordan Stefanov ◽  
Tino Ruland ◽  
Udo Schwalke
Keyword(s):  
Chemical Mechanical Planarization ◽  
Tunneling Current ◽  
Silicon Surfaces ◽  
Nanometer Scale ◽  
Shallow Trench Isolation ◽  
Force Microscopy ◽  
Atomic Force ◽  
Trench Isolation ◽  
Clear Identification ◽  
Non Destructive

ABSTRACTThis article proposes a new application of tunneling current measurements Atomic Force Microscopy (AFM) for evaluation of silicon nitride stop-layer erosion in Shallow Trench Isolation (STI) Chemical Mechanical Planarization (CMP). Simultaneous topographical and electrical AFM measurements allow a clear identification of ‘open’ silicon surfaces on nanometer scale by enhanced tunneling currents in those areas. The measurement technique is non-destructive and can be successfully implemented for process control.

Silicon Nitride Thickness Profile Tuning to Reduce Shallow Trench Isolation Variability in Planar CMOS

2016 ◽  
Vol 29 (3) ◽  
pp. 217-222
Author(s):  
Jaana Rajachidambaram ◽  
John Gumpher ◽  
Vineet Sharma ◽  
Chia Hao Tsao ◽  
Brett Yatzor
Keyword(s):  
Silicon Nitride ◽  
Shallow Trench Isolation ◽  
Thickness Profile ◽  
Trench Isolation

A Silicon Nitride Based Shallow Trench Isolation with Side-Gate for CMOS Integration with MEMS Components for System-On-Chip Applications

2004 ◽  
Vol 833 ◽  
Author(s):  
Ali Gokirmak ◽  
Sandip Tiwari
Keyword(s):  
Silicon Nitride ◽  
System On Chip ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Mems Resonators ◽  
High Temperature Anneal ◽  
Close Proximity ◽  
Trench Isolation ◽  
Electrostatic Control ◽  
On Chip

ABSTRACTWe have developed a hydrofluoric acid (HF) resistant, composite shallow trench isolation (STI) process for MOSFETs utilizing silicon nitride as isolation material for on-chip integration of micro-electro-mechanical (MEMS) resonators and CMOS devices. Peripheral leakage currents in silicon nitride isolated MOSFETs are suppressed by employing an independently controlled polysilicon side-gate, surrounding the active area of the devices. Electrostatic control of the threshold voltage at the device periphery alleviates the need for edge implants, resulting in increased thermal budget. Compatibility with HF release processes and high temperature anneal cycles allows integration of MEMS components in close proximity to CMOS devices for system-on-chip applications. nMOSFET devices fabricated using this composite STI process show excellent device characteristics.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Sign in / Sign up

Export Citation Format

Share Document