Global-to-Local Modeling and Experiment Investigation of HFCBGA Package Board-Level Solder Joint Reliability

2007 ◽  
Vol 4 (4) ◽  
pp. 186-194 ◽  
Author(s):  
C.I. Chen ◽  
S.C. Wu ◽  
D.S. Liu ◽  
C.Y. Ni ◽  
T. D. Yuan

Due to the high speed and high I/O count requirements for semiconductor packages, thousands of soldered interconnections are indispensable, and this situation renders traditional finite element method (FEM) analysis a formidable challenge. This paper presents a 3D-equivalent global model and local submodeling technique to investigate board-level solder joint reliability under cyclic temperature loading. The equivalent global model is capable of addressing critical solder failure locations. An individual local solder ball is used to predict the number of cycles to failure. The high performance flip-chip ball grid array (HFCBGA) package case was studied with the provided experimental data. According to FEM results, the predicted solder ball life is close to that observed experimentally. Therefore, the global-to-local modeling technique can be concluded to provide an efficient methodology for evaluating very high pin count HFCBGA package reliability.

2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman

2006 ◽  
Vol 504 (1-2) ◽  
pp. 426-430 ◽  
Author(s):  
Dae-Gon Kim ◽  
Jong-Woong Kim ◽  
Seung-Boo Jung

2018 ◽  
Vol 2018 (1) ◽  
pp. 000104-000109
Author(s):  
Mollie Benson ◽  
Burton Carpenter ◽  
Andrew Mawer

Abstract Radar is currently employed in automotive applications to provide the range, angle, and velocity of objects using RF waves (77GHz). This paper outlines solder joint reliability of a specific micro-processor that processes data received from a SRR (short range radar operating from 0.2 to 30 meters). It is a powerful digital signal processing accelerator, which targets safety applications that require a high Automotive Safety Integrity Level (ASIL-B). The paper explores the package design and construction, SMT (surface mount technology) assembly, and board level reliability testing of various BGA pad surface finish and solder ball alloy materials on a 0.65 mm pitch, 10 × 10 mm body 141 MAPBGA (mold array process-ball grid array) package. The package configurations include two BGA pad surface finishes (Ni/Au and OSP [organic solderability protectant]) and three solder alloys (SnAg, SAC405, and SAC-Bi [a Bi containing SAC derivative]). Solder joint reliability analysis was performed through AATS (air-to-air thermal shock) between 40°C and +125°C and JEDEC Drop Testing at 1500G's. Thermal shock was extended until at least 75% of the populations failed, which was well past the points needed to qualify the packages for the intended end-use applications. The evaluations of the micro-processor indicate that the MAPBGA package can meet the ASIL-B specification requirements with optimized combinations of BGA pad surface finish and solder alloy. The focus of this paper was to determine the baseline solder-joint thermal shock and JEDEC drop performance with varied BGA pad surface finish and solder ball alloy materials.


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