The European 3D Technology Platform (e-CUBES)

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000446-000501 ◽  
Author(s):  
Peter Ramm ◽  
Armin Klumpp ◽  
Josef Weber ◽  
Thomas Fritzsch ◽  
Maaike Taklo ◽  
...  
Keyword(s):  
System Integration ◽  
High Performance ◽  
Technological Development ◽  
Low Cost ◽  
Market Potential ◽  
3D Integration ◽  
3D Technology ◽  
Critical Dimensions ◽  
Technology Platform ◽  
Integration Technology

The European 3D technology platform that has been established represents the ensemble of 3D integration technologies which were developed within the e-CUBES project [http://www.ecubes.org]. It became evident that the fabrication of e-CUBES with their need for high-level miniaturization can only be realized by system integration technologies which use the third dimension. The main objective is to provide 3D integration technologies which on the one hand increase the performance sufficiently and at the same time allow for low cost fabrication in order to achieve products with a large market potential. The work was focussed on the requirements coming from application demonstrators. However, other requirements set by taking the visionary approach of developing strongly miniaturized micro/nano-systems were also a major task of the work. Research and technological development was necessary in the following fields in order to achieve the objectives. Seven corresponding technologies were successfully developed building a European platform on 3D Integration. This is considered to be essential output of the e-CUBES project. These are in the 3D integration categoriesVertical System Integration (3D-SOC): Fraunhofer IZM-M's Through-Si Via (TSV) Technology (ICV-SLID) and SINTEF's Hollow Via & Gold Stud Bump Bonding (HoViGo),Chip Stacking (3D-WLP): IMEC / Fraunhofer IZM's Thin-Chip-Integration Technology (TCI/UTCS) and CEA-LETI's Via Belt Technology, and3D Assembly (3D-SIP): 3D-PLUS' High Performance Package-in-Package (HiPPiP) and Wireless Die-on-Die (WDoD) Technologies, as well as Tyndall's Submicron Wire Anisotropic Conductive Film Technology (SW-ACF). Four optimized 3D integration technologies were successfully used in the development of three e-CUBES application demonstrators: Thin-Chip-Integration technology (TCI/UTCS) for Philips' Health & Fitness demonstrator, TSV technology ICV-SLID and HoViGo for Infineon's Automotive demonstrator (TPMS) and Package-in-Package technology HiPPiP for Thales' Aeronautic demonstrator. The 3D integration technologies which form part of the established e-CUBES platform will be presented including key characteristics, critical dimensions, electrical parameters and adaptability to new applications.

2.5D and 3D Integration Technology Update

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 1-35
Author(s):  
Robert Patti
Keyword(s):  
New Work ◽  
Customer Requirements ◽  
3D Integration ◽  
3D Technology ◽  
Integration Technology

This publication will cover Tezzaron's latest advancements in 2.5D and 3D technology including new wafer to wafer integration of InP and GaAs with CMOS devices and new work in bonded die to wafer assembly with sub 25um pitch. A manufacturing perspective of the evolving customer requirements and the unique challenges in testing these highly complex devices will be discussed.

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Engine Cycle Selection and Propulsion System Integration for Future High Performance Fighter Aircraft

1977 ◽  
Author(s):  
G. W. Lind ◽  
J. Protopapas
Keyword(s):  
System Integration ◽  
High Performance ◽  
Low Cost ◽  
Propulsion System ◽  
Fighter Aircraft ◽  
Performance Constraints ◽  
Design Variables ◽  
And Performance ◽  
Time Required ◽  
Engine Cycle

The selection and optimization of propulsion systems can be a costly and time-consuming process, especially when there are diverse performance requirements placed on the overall weapon system. Computerized procedures have been developed within the Grumman Propulsion Department to mechanize this capability and yet maintain the man-m-the-loop for full visibility during the evaluation of a candidate design concept. The system permits low cost, rapid, multidiscipline. interactive engine cycle selection and propulsion system integration to be effectively performed early in the preliminary design process of a high performance fighter aircraft. For example, the computer running time required to select a point design within a matrix of design variables and performance constraints has been reduced by 85 percent over previous techniques. This paper describes these propulsion evaluation procedures and cites a specific example of their application to the analysis of an advanced interceptor requirement.

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology

2011 ◽  
Vol 35 (4) ◽  
pp. 371-381 ◽  
Author(s):  
Hongbin Sun ◽  
Pengju Ren ◽  
Nanning Zheng ◽  
Tong Zhang ◽  
Tao Li
Keyword(s):  
Energy Efficient ◽  
High Performance ◽  
Soft Error ◽  
3D Integration ◽  
Error Resilient ◽  
Integration Technology

Die-on-Wafer and Wafer-Level Three-Dimensional (3D) Integration of Heterogeneous IC Technologies for RF-Microwave-Millimeter Applications

2004 ◽  
Vol 833 ◽  
Author(s):  
J.-Q. Lu ◽  
S. Devarajan ◽  
A. Y. Zeng ◽  
K. Rose ◽  
R. J. Gutmann
Keyword(s):  
High Performance ◽  
Three Dimensional ◽  
Wafer Level ◽  
3D Integration ◽  
3D Technology ◽  
Passive Components ◽  
Analog To Digital ◽  
Integration Platform ◽  
Rf Transceivers ◽  
Rf Microwave

ABSTRACTDie-on-wafer and wafer-level three-dimensional (3D) integrations of heterogeneous IC technologies are briefly described, emphasizing a specific 3D hyper-integration platform using dielectric adhesive wafer bonding and Cu damascene inter-wafer interconnects to provide a perspective on wafer-level 3D technology processing. Wafer-level 3D partitioning of high Q passive components, analog-to-digital (A/D) converters, RF transceivers, digital processors, and memory is discussed for high-performance RF-microwave-millimeter applications, especially where high manufacturing quantities are anticipated. Design and simulation results of 3D heterogeneous integration are presented. This 3D technology is applicable to smart wireless terminals, millimeter phased array radars, and smart imagers.

SI-ON-SI MCM TECHNOLOGY AND ITS APPLICATIONS

1991 ◽  
Vol 02 (04) ◽  
pp. 251-261 ◽  
Author(s):  
K.L. TAI
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Technological Development ◽  
High Reliability ◽  
Low Cost ◽  
Consumer Products ◽  
Printed Wiring Board ◽  
Cad System ◽  
Compact Size ◽  
Challenges And Opportunities

Multichip Module (MCM) packaging has been used in high-end systems, such as mainframe and supercomputers for some time. Rapid advances in VLSI technology and novel system architecture concepts have presented both challenges and opportunities for MCM technologists. We should not just try to find a solution, but also try to take a long-term view and plan the technological development. We would like to develop MCM technology which has a broad range of applications from consumer products to supercomputers. The technology should focus on low cost, high performance, compact size, and high reliability. We believe that it is most attractive to leverage IC technology and surface mount technology (SMT). Therefore we select Si wafer as the substrate, Al as the metallization, polyimide as the dielectrics, Ta-Si as the resistor material, and Si oxide and nitride as the dielectrics for capacitor. Flip-chip solder attachment are used to assemble chips on the substrate. We view our version of MCM as a “giant chip” rather than a miniaturized printed wiring board. This “giant chip” contains mixed device technologies which cannot be obtained by current device technology. The migration path should be from small to large module. The infrastructure of the CAD system and the testing system is critical for the development of MCM technology. Potential applications and implementations of MCM technology are given in this paper.

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