Versatile TIM Solution with Chain Network Solder Composite

2020 ◽  
Vol 2020 (1) ◽  
pp. 000264-000273
Author(s):  
Runsheng Mao ◽  
Sihai Chen ◽  
Elaina Zito ◽  
David Bedner ◽  
Ning-Cheng Lee
Keyword(s):  
Flip Chip ◽  
Filler Content ◽  
Solder Paste ◽  
High Melting ◽  
Liquid Solder ◽  
Reflow Process ◽  
Cu Content ◽  
Sufficient Concentration ◽  
Sac Solder ◽  
Solder Composite

ABSTRACT A novel epoxy-based SAC solder paste TIM system has been developed with the use of non-volatile epoxy flux. Cu filler was added to the solder paste, with Cu volume % of metal ranged from 17 to 60 volume % of metal. Formation of semi-continuous high melting Cu chain network was achieved, with Cu particles bridged by the CuSn IMC. This chain network, at sufficient concentration, serves as skeleton and maintains the shape of the sandwiched solder paste layer, thus prevents further spread out at subsequent SMT reflow process, and also allowed formation of TIM joint even in the absence of solderable metallization on flip chip and packaging housing. This chain network hampered the flow of liquid solder, thus restrained the expansion of outgassing, and consequently resulted in low voiding. Existence of crevices was attributed to excessive oxide brought in by Cu particles, and appeared to increase with increasing Cu filler content. Presence of ductile solder within TIM joint promises high resistance against brittle cracking under stress. The Cu content could be further optimized between 17 and 33 volume % of metal to avoid flux bleeding and maintain good epoxy adhesion between TIM phase and parts. The 20°C thermal conductivity achieved was 6.1 W/mK, and could be up to about 13 W/mK with further epoxy flux optimization.

Reliability of electronics assembled using SAC + Zn solder pastes

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000051-000057 ◽  
Author(s):  
H.R. Kotadia ◽  
A. Panneerselvam ◽  
M.A. Green ◽  
M.P. Clode ◽  
S.H. Mannan ◽  
...  
Keyword(s):  
Solder Alloy ◽  
Electroless Nickel ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Reflow Process ◽  
Reliable Operation ◽  
Interfacial Imcs ◽  
Electroless Nickel Immersion Gold ◽  
Reliability Of Electronics ◽  
Sac Solder

A method of preparing SAC solder with addition of 1.0-1.5wt.% Zn to Sn-3.8Ag-0.7Cu solder alloy such that a standard solder paste reflow process results in good soldering is described. Solder-substrate couples were aged at 150°C for 1000h, and results on temperature cycling (−20 to 175°C) and shear testing of solder joints is also described. The added Zn segregated to the interfacial IMCs so that Cu6Sn5 became (Cu,Zn)6Sn5 and (Cu,Ni)6Sn5 became (Cu,Ni,Zn)6Sn5. The reliability of assemblies utilizing Electroless Nickel Immersion Gold (ENIG) using the Zn enhanced solder is compared to that of standard SAC solder alloy for potentially reliable operation at temperature up to 185°C.

Wettability of CNT-Doped Solder under Isothermal Aging

2016 ◽  
Vol 857 ◽  
pp. 76-78
Author(s):  
Norliza Ismail ◽  
Roslina Ismail ◽  
Nur Izni Abd Aziz ◽  
Azman Jalar
Keyword(s):  
Carbon Nanotubes ◽  
Contact Angle ◽  
Isothermal Aging ◽  
Optical Microscope ◽  
Image Analyzer ◽  
Solder Paste ◽  
Reflow Process ◽  
Weight Percentage ◽  
Test Board ◽  
Free Solder

Wettability for lead free solder 99.0Sn-0.3Ag-0.7Cu (SAC237) with addition of different weight percentage carbon nanotube after thermal treatment was investigated. SAC 237 solder powder with flux was mixed with 0.01%, 0.02%, 0.03% and 0.04% carbon nanotubes (CNTs) to form SAC-CNTs solder paste. Printed solder paste on test board with Cu surface finish was then reflow under 270°C temperature and isothermal aging at 150°C for 0,200 and 400 hours. Wettability of SAC-CNT solder was determined by measuring contact angle using optical microscope and image analyzer. As a result, from reflow process right through 400 hours of thermal aging, SAC237 with 0.04% CNT has the lowest contact angle as compared to other SAC-CNTs and SAC237 solder. As a conclusion, addition of carbon nanotubes into solder SAC237 improved their wettability on Cu substrate, especially at 0.04% of CNTs.

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Ultra-low Residue Flux Applications in RF Front-End Packages

2020 ◽  
Vol 2020 (1) ◽  
pp. 000125-000130
Author(s):  
Leo Hu ◽  
Sze Pei Lim
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Reflow Process ◽  
Reliability Study ◽  
Rf Switches ◽  
Front End ◽  
Rf Front End ◽  
Package Reliability

Abstract With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000671-000707
Author(s):  
Stephen Kenny ◽  
Sven Lamprecht ◽  
Kai Matejat ◽  
Bernd Roelfs
Keyword(s):  
Flip Chip ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Advantages And Disadvantages ◽  
Novel Approach ◽  
Solder Bumps ◽  
Chip Attachment

Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.

Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-18
Author(s):  
Phani Vallabhajosyula
Keyword(s):  
Visual Inspection ◽  
Flip Chip ◽  
Print Quality ◽  
Solder Paste ◽  
3D Measurement ◽  
Aperture Size ◽  
Fine Pitch ◽  
Technology Applications ◽  
Component Assembly ◽  
Special Step

Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. However as SMT requirements became more complex and consequently more demanding so did the requirements for complex Step Stencils. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 40um with steps of 13um are used to obtain desired print volume. These applications and the associated stencil design to achieve a solution will be discussed in detail in this paper. Various print experiments will be conducted and print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.

Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids

2017 ◽  
Vol 2017 (1) ◽  
pp. 000201-000207 ◽  
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Hearing Aids ◽  
Flip Chip ◽  
Failure Modes ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Practical Application ◽  
Surface Mount ◽  
Free Solder ◽  
On Chip

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Considerable amount of defects associated with solder overflow are found on chip-on-flip-chip (COFC) SiP in hearing aids. Through the use of design of experiments (DOE), lead-free solder defect causes on hearing aids application can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components for hearing aid applications. The practical application and analysis of lead-free solder for hearing aids will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types through the DOE process.

Comparative Modeling and Analysis of Lead-Free Solder Extrusion for the Design of Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000111-000116
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Design Of Experiments ◽  
Flip Chip ◽  
Failure Modes ◽  
Form Factors ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Modeling And Analysis ◽  
Surface Mount ◽  
Free Solder

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Through the use of design of experiments (DOE), lead-free solder defect causes can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components. The systematic investigation will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types utilizing the design of experiments methods.

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