Ultra-low Residue Flux Applications in RF Front-End Packages

2020 ◽  
Vol 2020 (1) ◽  
pp. 000125-000130
Author(s):  
Leo Hu ◽  
Sze Pei Lim

Abstract With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

2019 ◽  
Vol 2019 ◽  
pp. 1-11 ◽  
Author(s):  
Haider Ali ◽  
Anwar Ali ◽  
M. Rizwan Mughal ◽  
Leonardo Reyneri ◽  
Claudio Sansoe ◽  
...  

In recent years, the development market for low-cost nanosatellites has grown considerably. It has been made possible due to the availability of low-cost launch vectors and the use of “commercial off-the-shelf components” (COTS). The satellite design standardization has also helped a great deal to encourage subsystem reuse over a number of space missions. This has created numerous opportunities for small companies and universities to develop their own nanosatellite or satellite subsystems. Most COTS components are usually not space qualified. In order to make them work and withstand the harsh space environment, they need extra effort in circuit redesign and implementation. Also, by adopting the modularity concept and the design reuse method, the overall testing and nonrecurring development cost can be significantly reduced. This can also help minimize the subsystem testing times. The RF front-end design presented in this paper is also considered one of the better and feasible choices based on the above approach. It consists of an S-band transceiver that is fully implemented using COTS components. In the transmit chain, it is comprised of the transmitting CC2510 RF matching network and a power amplifier (PA) with an RF output power of up to 33 dBm which connects to an antenna using two RF switches. The receive chain starts from the antenna that is connected through two RF switches to the low-noise amplifier (LNA) that further connects to the receiving CC2510 via the RF matching network. The receiver sensitivity is -100 dBm. This is a half-duplex system using the same antenna for transmitting and receiving. The receiver and transmitter chains are isolated together using two RF switches which together provide an isolation of up to 90 dB at 2.4 GHz. The concept behind using two RF switches is to provide better isolation from the transmit chain to the LNA. The matching network of CC2510 has been designed in a symmetric fashion to avoid any delays. All the RF COTS used have been selected according to link budget requirements. The LNA, PA, and RF switches were tested individually for compliance. The passive components used in the overall design of the matching network are chosen on the basis of minimum dimension, least parasitic behaviour, and guaranteed optimum RF matching. Also, the RF COTS used are non-CMOS which makes them more robust against space radiations associated with the LEO environment and enables them to provide a radio communication data rate of up to 500 kbps in both uplink and downlink. The vacant spaces on the implemented PCB are shielded with a partial ground plane to avoid RF interference.


2015 ◽  
Vol 7 (3-4) ◽  
pp. 307-315 ◽  
Author(s):  
Marc van Heijningen ◽  
Jeroen A. Hoogland ◽  
Peter de Hek ◽  
Frank E. van Vliet

The front-end circuitry of transceiver modules is slowly being updated from GaAs-based monolithic microwave integrated circuits (MMICs) to Gallium-Nitride (GaN). Especially GaN power amplifiers and T/R switches, but also low-noise amplifiers (LNAs), offer significant performance improvement over GaAs components. Therefore it is interesting to also explore the possible advantages of a GaN mixer to enable a fully GaN-based front-end. In this paper, the design-experiment and measurement results of a double-balanced image-reject mixer MMIC in 0.25 μm AlGaN/GaN technology are presented. First an introduction is given on the selection and dimensioning of the mixer core, in relation to the linearity and conversion loss. At the intermediate frequency (IF)-side of the mixer, an active balun has been used to compensate partly for the loss of the mixer. An on-chip local-oscillator (LO) signal amplifier has been incorporated so that the mixer can function with 0 dBm LO input power. After the discussion of the circuit design the measurement results are presented. The performance of the mixer core and passive elements has been demonstrated by measurements on a test-structure. The mixer MMIC measured conversion loss is <8 dB from 6 to 12 GHz, at 1 GHz IF and 0 dBm LO power. The measured image rejection is better than 30 dB.


Author(s):  
Gianluca Cornetta ◽  
David J. Santos ◽  
José Manuel Vázquez

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.


Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.


Author(s):  
Ilku Nam ◽  
Donggu Im ◽  
Young-Wook Lim ◽  
Xuemin Xu ◽  
Hyung Su Lee ◽  
...  

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