High Productivity Thermo-Compression Flip Chip Bonding

2014 ◽  
Vol 2014 (1) ◽  
pp. 000100-000106
Author(s):  
Tom Colosimo ◽  
Horst Clauberg ◽  
Evan Galipeau ◽  
Matthew B. Wasserman ◽  
Michael Schmidt-Lange ◽  
...  

Advancements in electronic packaging performance and cost have historically been driven by higher integration primarily provided by fab shrinks that has followed the well-known Moore's law. However, due to the tremendous and continuously increasing cost of building new fabs, the performance/cost improvements achieved via node shrinks are negated. This leaves packaging innovation as the vehicle to achieve future cost-performance improvements. This has initiated a More-than-Moore idea that has led to vigorous R&D in packaging. Advanced packages which employ ultra-fine pitch flip chip technology for chip-to-substrate, chip-to-chip, or chip-to-interposer for the first level interconnect have been developed as an answer to obtaining higher performance. However, the costs are too high as compared to traditional wire bonding. The status today is that the fundamental technical hurdles of manufacturing the new advanced packages have been solved, but cost reduction and yield improvements have to be addressed for large-scale adoption into high volume manufacturing. In traditional flip chip assembly silicon chips are tacked onto a substrate and then the solder joints are melted and mass reflowed in an oven. This mass reflow technique is troublesome as the pitch of the solder bumps become finer. This is due to the large differences in the thermal expansion coefficient of the die and the substrate, which creates stress at the solder joints and warpage of the package when the die and substrate are heated and cooled together. To mitigate and resolve this issue, thermo-compression bonders have been developed which locally reflow the solder without subjecting the entire substrate to the heating and cooling cycle. This requires that the bondhead undergo heating past the melting point of solder and then cooling down to a low enough temperature to pick the next die from the wafer that is mounted to tape. Machines in the market today can accomplish this temperature cycle in 7 to 15 seconds. This is substantially slower than the standard flip chip process which leads to high cost and is delaying the introduction of these new packages. This paper shows a flip chip bonder with a new heating and cooling concept that will radically improve the productivity of thermo-compression bonding. Data and productivity cycles from this new bond head with heating rates of over 200°C/sec and cooling of faster than 100°C/sec are revealed. Experimental results are shown of exceptional temperature accuracy across the die of 5°C throughout the cycle and better than 3°C at the final heating stage. The high speed thermo-compression bonds are analyzed and the efficacy of the new concept is proven. Excellent temperature uniformity while heating rapidly is an absolute necessity for enabling good solder joints in a fast process. Without good temperature uniformity, additional dwell times need to be incorporated to allow heat to flow to all of the joints, negating any benefits from rapid heating. Whereas the current state-of-that-art is often to program temperature in steps, this bonder can be commanded and accurately follows more complex temperature profiles with great accuracy. Examples of how this profiling can be used to enhance the uniformity and integrity of the joints with non-conductive pastes, film, and without underfill along with the associated productivity improvements will be shown. Tests that show portability across platforms that will lead to set up time and yield improvements and are identified and quantified. Additionally new ideas for materials and equipment development to further enhance productivity and yield are explored.

Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.


2013 ◽  
Vol 284-287 ◽  
pp. 375-379 ◽  
Author(s):  
Chieh Kung

System-in-package (SiP) has become a mainstream technology in IC package industry as it provides the solutions to the growing needs of high speed functions, mobility/portability, energy efficiency, and miniaturization of electronic products. One special form of SiP is the multi-chip module (MCM) in which multiple integrated circuits (ICs), semiconductor dies or other discrete components are packaged onto a unifying substrate. Thus, the reliability of package integrity becomes one of the major reliability concerns. In the present paper, a robust design analysis on the thermo-mechanical reliability of an MCM package with flip-chip technology is demonstrated. Our results show that for the specific package, the CTE of the substrate is the most influential factor to the fatigue reliability of the package. The optimal combination of the parameters is recommended. The robust design analysis optimizes the fatigue life from 165 cycles to 1080 cycles which is a 554.5% gain on the fatigue life.


2009 ◽  
Vol 6 (1) ◽  
pp. 38-41
Author(s):  
Lewis Dove

Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.


2009 ◽  
Vol 23 (06n07) ◽  
pp. 1809-1815 ◽  
Author(s):  
SANG-SU HA ◽  
SANG-OK HA ◽  
JIN-KYU JANG ◽  
JONG-WOONG KIM ◽  
JONG-BUM LEE ◽  
...  

The failure behaviors of flip chip solder joints under various loading conditions of the high-speed shear test (H-SST) were investigated with an experimental and non-linear 3-dimensional finite element modeling study. The solder composition used in this study was Sn -3.0 Ag -0.5 Cu ( in wt .%). The shear forces were far greater by H-SST than by low-speed shear test (L-SST). The shear force further increased with increasing shear speed, mainly due to the high strain-rate sensitivity of the solder alloy. Brittle interfacial fractures were more easily achieved by H-SST, especially at the higher shear speed. This was discussed in terms of the relationship between the strain-rate and work-hardening effect and the resulting stress concentration at the interfacial regions


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000944-000967
Author(s):  
Takeshi Hatta ◽  
Atsushi Ishikawa ◽  
Takuma Katase ◽  
Akihiro Masuda

Flip chip connection has been applied to a lot of applications to shorten the connection length for high performance. Solder bumping is one of the key technologies for flip chip connection, and its quality strongly brings large impact on the reliability after packaging. Electroplating is one of the methods to form solder bumps. And Sn-Ag is considered as the first candidate of lead free alloy for electroplating method. We have released Sn-Ag plating chemical and it has been used by many customers in the world. In the future, flip chip technology will progress to further miniaturization and high integration with the new technologies such as Cu pillar and Through Silicon Via (TSV). At that time, further variations of alloys are necessary for electroplating method to meet various requirements. Even for Sn-Ag plating chemical, higher plating rate is required to improve productivity in mass production. In this time, we have developed new Sn-Ag high speed plating chemical based on our conventional technology. Furthermore, we have succeeded to develop Pure Sn and Sn-Cu chemicals for bumping method to meet customer's requirement. Sn-Cu is considered as a good candidate for bumping alloy to achieve high reliability, but the chemical stability is not so good. Therefore, we successfully modified the Sn-Cu chemical and extended chemical stability. We will update our current status about high speed Sn-Ag plating chemical and other chemicals like Sn-Cu and pure Sn in this time. By using these binary alloy chemicals, we are able to produce Sn-Ag-Cu solder bumps by stacking Sn-Ag and Sn-Cu. And it can bring further variation for bumping alloys.


2011 ◽  
Vol 189-193 ◽  
pp. 1009-1013 ◽  
Author(s):  
Yu Dong Lu ◽  
Yun Fei En ◽  
Ming Wan ◽  
Xiao Qi He ◽  
Xin Wang

A frequent cause of failure of portable and hand-held devices is an accidental drop to the ground. The effect of electromigration on the mechanical properties of solder joints was discussed in this paper. Without current stressing, the samples were broken in the bulk of solder or at the interface of Al interconnect and solder. If the Al-solder interfacial mechanical strength was improved by changed the interfacial structure or optimized the jointing process, the flip chip devices would show the lonely ductile fracture in the bulk of solder. After electromigration the samples were broken abruptly at the interface near the chip side while the bulk of the solder joints maintained the original shape. Due to the interfacial reaction and the polarity effect of electromigration on the interfaces, a ductile solder joint can become a brittle solder joint. The ductile-to-brittle transition is very sensitive to a high speed shear stress applied to the joints. Because solder alloys are ductile by nature, it is of interest to understand how electromigration can influence the mechanical properties of solder joints’ interfaces and change their ductile nature. Owing to the polarity effect of electromigration, vacancies will accumulate to form voids at the cathode interface of solder joints. Besides, much more intermetallic compound formation at the joint interfaces also caused the ductile-to-brittle transition. Thus the interfaces become more and more brittle with time due to IMC formation or vacancy accumulation from electromigration.


2005 ◽  
Vol 128 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Wen-Hwa Chen ◽  
Shu-Ru Lin ◽  
Kuo-Ning Chiang

An accurate and efficient analytical geometric method is presented for predicting the geometric parameters of the controlled collapse chip connection type solder joint using direct chip attach technology after a reflow process. By this method, the meridian of the solder joint is first discretized as a series of sufficiently fine fragmental arcs. After calculating the internal pressure inside the molten eutectic solder from the forces balance, the meridional and circumferential radii of curvature of each arc are then obtained from the Laplace-Young equation. As a result, the coordinates of each node of the arc and the solder joint geometry can be determined in turn. The factors that affect the final shape of the molten eutectic solder joints, including the solder volumes, external loading, pad size, surface tension of molten eutectic solder, and interfacial surface tension between the molten eutectic solder and the solid high-lead bump are considered herein. The results computed by the analytical geometric method are also compared with those obtained using the Surface Evolver program, the extended Heinrich’s model, and the experimental results. The results of the various approaches are mutually consistent.


Sign in / Sign up

Export Citation Format

Share Document