FAILURE ANALYSIS OF DISCOLORED ENIG PADS IN THE MANUFACTURING ENVIRONMENT

2014 ◽  
Vol 2014 (1) ◽  
pp. 000653-000661
Author(s):  
Monika Marciniak ◽  
Michael Meagher ◽  
Jon Davis ◽  
Jack Josefowicz
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Boards ◽  
Electroless Nickel ◽  
Manufacturing Environment ◽  
Electron Microscopic ◽  
Verification Method ◽  
Surface Finishes ◽  
Line Process ◽  
Cleaning Methods ◽  
Surface Examination

Manufacturing of electronic assemblies using printed circuit boards (PCBs) with electroless nickel/immersion gold (ENIG) surface finishes requires front-end PCB evaluation that will guarantee that good quality product enters the assembly line. The most common is an IPC-4552 mandated plating thicknesses verification of 3-6μm and a minimum of 0.05μm for nickel and gold, respectively. Coupled with visual examination, this verification method suffices for general PCB acceptance but may not be robust enough in cases where ENIG plating in PCBs is compromised. That poses challenges in the manufacturing environment, where resulting latent defects are detected in downstream processes but not at upfront incoming inspection. Manifestation of such latent anomaly was observed in the form of ENIG pad discoloration with variations from yellow, red or grey discolored surfaces to a more pronounced plating degradation, such as corrosive pitting. The launched failure analysis involved evaluation of manufacturing processes suspected to contribute to the cause of the condition. Effects of thermal processes, cleaning methods, soldering, parylene deposition and factory cleanliness were examined thoroughly. Concurrently, metallurgical analysis of ENIG pads was performed, where samples were subjected to scanning electron microscopic/energy dispersive x-ray spectroscopic (SEM/EDX) cross section analysis, Auger electron spectroscopy (AES) and gold (Au) and electroless nickel (Ni) surface examination. The resulting analysis revealed a highly porous electroless nickel coating with deep crevasses and fissures penetrating down to the base copper (Cu) layer. These open nickel boundaries were attributed to the corrosive environment within ENIG plating, which resulted in the pad surface discoloration. The root cause of ENIG pad discoloration and pitting was traced back to poor ENIG line process controls. Subsequent introduction of a nickel controller into the ENIG line were the implemented countermeasures. To mitigate the effects of discoloration at the electronic assembly level, a tinning process was implemented to prevent nickel plating oxidation and to ensure that good wettability for reliable solder joints was maintained.

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

A STUDY OF SURFACE FINISHES FOR IC SUBSTRATES AND WIRE BOND APPLICATIONS

2011 ◽  
Vol 2011 (1) ◽  
pp. 000516-000520 ◽  
Author(s):  
John Ganjei ◽  
Ernest Long ◽  
Lenora Toscano
Keyword(s):  
Surface Finish ◽  
Printed Circuit Boards ◽  
Performance Enhancement ◽  
High Reliability ◽  
Cost Effective ◽  
Electroless Nickel ◽  
Gold Wire ◽  
Electronics Industry ◽  
Surface Finishes ◽  
And Performance

The continuing drive for ever increasing performance enhancement in the electronics industry, in combination with the recent, very significant increase in precious metal costs have left fabricators and OEMs questioning what the best, most cost effective, surface finish is for high reliability applications. Currently, the IC substrate market relies heavily on electrolytic nickel and gold as a solderable and superior wire bondable surface. The use of this finish has allowed manufacturers to avoid the reliability concerns However, this choice also results in significant design restraints being imposed. Many in the industry are now investigating the use of electroless nickel/electroless palladium/immersion gold (ENEPIG) to achieve both high reliability and performance, without the negative design restraints imparted by the use of electrolytic processes. However, over the last year alone, the industry has watched the price of gold increase by 50% and that of palladium double [1]. With this in mind, and considering the historic precedent set in the mid 1990’s when ENEPIG was also evaluated as a surface finish for printed circuit boards, when coincidentally, the cost of palladium also reached an all time high, it should be remembered that the electronics industry quickly moved to evaluate alternate, more cost sustainable, surface finishes. This paper details the use of lower cost, alternate surface finishes for IC substrate applications, with particular experimental focus on gold wire bonding capabilities and BGA solderability of the finishes described. The paper also discusses related process cycle advantages and the significantly reduced operating costs associated with these new finishes.

Plating reliability and high frequency testing of DuPont™ GreenTape™ 9K7 LTCC

2013 ◽  
Vol 2013 (1) ◽  
pp. 000678-000682
Author(s):  
Allan Beikmohamadi ◽  
Patricia Graddy ◽  
Deepukumar Nair ◽  
Jim Parisi ◽  
Steve Stewart
Keyword(s):  
Thick Film ◽  
High Frequency ◽  
Electroless Nickel ◽  
Test Methods ◽  
Substantial Improvement ◽  
Standard Test ◽  
Low Dielectric ◽  
Industry Standard ◽  
Joint Reliability ◽  
Surface Finishes

Low Temperature Co-fired Ceramic (LTCC) with low dielectric loss is suitable for use on microwave and millimeter wave circuits. Thick film gold or silver conductors are used as metallization on LTCC substrates. Gold prices are increasing at a rapid rate, so efforts were made to lower the dependency on gold by substituting silver with Ni/Au surface finishes as the top conductor. The external thick film silver conductors were plated using a standard Electroless Nickel Immersion Gold (ENIG) process. The Ni/Au surface finishes provides substantial improvement to fretting corrosion, environmental protection, contact resistance, wire bond strengths, solder ability and solder joint reliability. The reliability testing of DuPont™ GreenTape™ 9K7 LTCC with Ni/Au surface finishes is being conducted. The reliability test methods & conditions were chosen from well-established industry standard test protocols. This paper reports the reliability and high frequency testing results on the ENIG plated GreenTape™ 9K7 LTCC system.

Mechanical Test of FPCB and Failure Analysis by Simulation

2009 ◽  
Author(s):  
Jian Zhong ◽  
Ping Yang ◽  
Jian-ping Li ◽  
Hai-bo Sun ◽  
Quayle Chen ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Boards ◽  
Simulation Analysis ◽  
Mechanical Test ◽  
Mechanical Tests ◽  
Stress Distributions ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Depth Analysis ◽  
Flexible Printed Circuit

The paper mainly presented mechanical test and failure analysis methods to reliability study of a new FPCB (Flexible Printed Circuit Boards). Mechanical tests include flexural test, tensile test and flexural fatigue and ductility test. As to simulation analysis, the stress distributions of FPCB under bending and tensile conditions were gained by simulations. Through in-depth analysis of the testing results, the mechanical reliability of FPCB was known detailed. The research provides an approach to improve FPCB performance.

The formation of intermetallic layer structure of SAC405/Cu and SAC405/ENImAg solder joint interfaces

2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Rabiatul Adawiyah Mohamed Anuar ◽  
Saliza Azlina Osman
Keyword(s):  
Shear Strength ◽  
Surface Finish ◽  
Printed Circuit Boards ◽  
Solder Joints ◽  
Layer Structure ◽  
Ageing Time ◽  
Intermetallic Layer ◽  
Electroless Nickel ◽  
Optical Microscope ◽  
Content Type

Purpose The surface finish is an essential step in printed circuit boards design because it provides a solderable surface for electronic components. The purpose of this study to investigate the effects of different surface finishes during the soldering and ageing process. Design/methodology/approach The solder joints of Sn-4.0Ag-0.5Cu/Cu and Sn-4.0Ag-0.5Cu/electroless nickel/immersion silver (ENImAg) were investigated in terms of intermetallic (IMC) thickness, morphology and shear strength. The microstructure and compositions of solder joints are observed, and analyzed by using scanning electron microscopy (SEM-EDX) and optical microscope (OM). Findings Compounds of Cu6Sn5 and (Cu, Ni)6Sn5 IMC were formed in SAC405/Cu and SAC405/ENImAg, respectively, as-reflowed. When the sample was exposed to ageing, new layers of Cu3Sn and (Ni, Cu)3Sn5 were observed at the interface. Analogous growth in the thickness of the IMC layer and increased grains size commensurate with ageing time. The results equally revealed an increase in shear strength of SAC405/ENImAg because of the thin layer of IMC and surface finish used compared to SAC405/Cu. Hence, a ductile fracture was observed at the bulk solder. Overall, the ENImAg surface finish showed excellent performance of solder joints than that of bare Cu. Originality/value The novel surface finish (ENImAg) has been developed and optimized. This alternative lead-free surface finish solved the challenges in electroless nickel/immersion gold and reduced cost without affecting the performance.

Reliability Study and Failure Analysis for Surface Finishes on Sn–Ag–Cu Solder Joints During Thermal Cycling

2016 ◽  
Vol 3 (4) ◽  
pp. 269-275
Author(s):  
Chaobo Shen ◽  
Zhou Hai ◽  
Cong Zhao ◽  
Jiawei Zhang ◽  
John L. Evans ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Thermal Cycling ◽  
Solder Joints ◽  
Reliability Study ◽  
Surface Finishes

Failure analysis of printed circuit boards in the main telephone system of marine product factory

2016 ◽  
Vol 62 ◽  
pp. 300-305 ◽  
Author(s):  
Masamitsu Watanabe ◽  
Masaaki Takaya ◽  
Morihiko Matsumoto ◽  
Jun'ichi Sakai
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Boards ◽  
Circuit Boards ◽  
Printed Circuit ◽  
Telephone System ◽  
Marine Product

Nanoprobing and EBAC for Improving Failure Analysis Success Rates on Sub-14nm Logic and SRAM

2018 ◽  
Author(s):  
John Masnik ◽  
Noor Jehan Saujauddin ◽  
Kevin Davidson ◽  
Esther P.Y. Chen
Keyword(s):  
High Resolution ◽  
Failure Analysis ◽  
Case Studies ◽  
Electrical Measurement ◽  
Success Rates ◽  
Electron Microscopic ◽  
Microscopic Scale ◽  
Static Technique

Abstract Nanoprobing, electrical probing (DC electrical measurement of semiconductors using nanoscale probes) on an electron microscopic scale, and EBAC, a high-resolution, static technique, can be used for isolating defects and improving failure analysis success rates on both logic and SRAM devices. This paper presents three case studies of subtle defects on a technology beyond 14nm that required nanoprobing.

Sign in / Sign up

Export Citation Format

Share Document