Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.


2014 ◽  
Vol 2014 (1) ◽  
pp. 000653-000661
Author(s):  
Monika Marciniak ◽  
Michael Meagher ◽  
Jon Davis ◽  
Jack Josefowicz

Manufacturing of electronic assemblies using printed circuit boards (PCBs) with electroless nickel/immersion gold (ENIG) surface finishes requires front-end PCB evaluation that will guarantee that good quality product enters the assembly line. The most common is an IPC-4552 mandated plating thicknesses verification of 3-6μm and a minimum of 0.05μm for nickel and gold, respectively. Coupled with visual examination, this verification method suffices for general PCB acceptance but may not be robust enough in cases where ENIG plating in PCBs is compromised. That poses challenges in the manufacturing environment, where resulting latent defects are detected in downstream processes but not at upfront incoming inspection. Manifestation of such latent anomaly was observed in the form of ENIG pad discoloration with variations from yellow, red or grey discolored surfaces to a more pronounced plating degradation, such as corrosive pitting. The launched failure analysis involved evaluation of manufacturing processes suspected to contribute to the cause of the condition. Effects of thermal processes, cleaning methods, soldering, parylene deposition and factory cleanliness were examined thoroughly. Concurrently, metallurgical analysis of ENIG pads was performed, where samples were subjected to scanning electron microscopic/energy dispersive x-ray spectroscopic (SEM/EDX) cross section analysis, Auger electron spectroscopy (AES) and gold (Au) and electroless nickel (Ni) surface examination. The resulting analysis revealed a highly porous electroless nickel coating with deep crevasses and fissures penetrating down to the base copper (Cu) layer. These open nickel boundaries were attributed to the corrosive environment within ENIG plating, which resulted in the pad surface discoloration. The root cause of ENIG pad discoloration and pitting was traced back to poor ENIG line process controls. Subsequent introduction of a nickel controller into the ENIG line were the implemented countermeasures. To mitigate the effects of discoloration at the electronic assembly level, a tinning process was implemented to prevent nickel plating oxidation and to ensure that good wettability for reliable solder joints was maintained.


Author(s):  
Todd Castello ◽  
Dan Rooney ◽  
Dongkai Shangguan

Abstract Printed circuit board assembly with lead free solder is now a reality for most global electronics manufacturers. Extensive research and development has been conducted to bring lead free assembly processes to a demonstrated proficiency. Failure analysis has been an integral part of this effort and will continue to be needed to solve problems in volume production. Many failure analysis techniques can be directly applied to study lead free solder interconnects, while others may require some modification in order to provide adequate analysis results. In this paper, several of the most commonly applied techniques for solder joint failure analysis will be reviewed, including visual inspection, x-ray radiography, mechanical strength testing, dye & pry, metallography, and microscopy/photomicrography, comparing their application to lead bearing and lead free solder interconnects. Common failure modes and mechanisms will be described with examples specific to lead free solders, following PCB assembly as well as after accelerated reliability tests.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Sandeep Menon ◽  
Adam Pearl ◽  
Michael Osterman ◽  
Michael Pecht

Surface finishes are used to preserve and promote solderability of exposed copper metallization on printed wiring boards. While in the best of worlds, the solder used in assembly should dictate the solder interconnect reliability, surface finishes are known to have an effect. The effect of surface finishes on solder interconnect reliability can be particularly strong under high strain rate loading conditions. In this study, durability of solder interconnects formed between BGAs and electroless nickel, electroless palladium, immersion gold (ENEPIG) finished pads assembled using SnPb and SAC305 solders under harmonic vibration loading is examined. ENEPIG test specimens with two thicknesses of palladium were evaluated. Isothermal preconditioning levels at 100°C for 24 hrs and 500 hrs were included to evaluate the impact of intermetalic evolution on the durability of the soldered interconnects. For comparison, tests specimens created with immersion silver (ImAg) finished printed wiring boards were also included. The failure data obtained found the durability of interconnects formed with ENEPIG finish was comparable or better durability than the durability of interconnects formed with ImAg finish irrespective of the solder. The tests indicate that the use of a thicker palladium layer reduced the degradation in durability which occurred from isothermal aging.


2021 ◽  
Author(s):  
Kuang-Tse Ho ◽  
Cheng-Che Li

Abstract This research summarizes a variety of physical failure modes of GaAs-based oxide-confined VCSELs and their root causes. Standard failure analysis procedure, which includes defect fault isolation by PEM or IR-OBIRCH and physical inspection by TEM analysis are also presented in detail.


Author(s):  
Kuang-Tse Ho ◽  
Ching-Hsiang Chan

Abstract This research summarizes a variety of physical failure modes of GaAs-based oxide-confined VCSELs and their root causes. Standard failure analysis procedure, which includes defect fault isolation by PEM or IR-OBIRCH and physical inspection by TEM analysis are also presented in detail.


Author(s):  
Erick Kim ◽  
Kamjou Mansour ◽  
Gil Garteiz ◽  
Javeck Verdugo ◽  
Ryan Ross ◽  
...  

Abstract This paper presents the failure analysis on a 1.5m flex harness for a space flight instrument that exhibited two failure modes: global isolation resistances between all adjacent traces measured tens of milliohm and lower resistance on the order of 1 kiloohm was observed on several pins. It shows a novel method using a temperature controlled air stream while monitoring isolation resistance to identify a general area of interest of a low isolation resistance failure. The paper explains how isolation resistance measurements were taken and details the steps taken in both destructive and non-destructive analyses. In theory, infrared hotspot could have been completed along the length of the flex harness to locate the failure site. However, with a field of view of approximately 5 x 5 cm, this technique would have been time prohibitive.


Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.


Author(s):  
J.G. van Hassel ◽  
Xiao-Mei Zhang

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.


Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.


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