scholarly journals Vedic Multiplier Implementation for High Speed Factorial Computation

2012 ◽  
Vol 1 (04) ◽  
pp. 01-06
Author(s):  
Prof. Sharayu Waghmare
Keyword(s):  
Comparative Analysis ◽  
High Speed ◽  
Vlsi Architecture ◽  
Path Delay ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
The Given ◽  
Mathematical Operations ◽  
Indian Mathematics

Vedic Mathematics arise from the prehistoric classification of Indian mathematics that was recreated by Tirthaji. Ancient mathematical operations are depending on sixteen methods. In this article, a new VLSI architecture to compute factorial of the given number with Vedic based multiplier is proposed. Simulations are performed using Xilinx ISE 14.2. Effective comparative analysis is made with existing multipliers to prove the momentous development in competence and high speed operation. This efficient multiplier is implemented in the proposed factorial architecture which significantly reduces the path delay and provides better optimization.

scholarly journals The Issue of Criticizing the Text of the Short Story ʽWhere Love Is, There God Is Also’ by Leo Tolstoy (1885)

2021 ◽  
Vol 3 (1) ◽  
pp. 244-261
Author(s):  
Irina I. Sizova
Keyword(s):  
Comparative Analysis ◽  
Short Story ◽  
Final Stage ◽  
Research Literature ◽  
Main Text ◽  
Textual Practice ◽  
History Of ◽  
The Given ◽  
History Of Formation

The article is devoted to the issue of criticizing the text of Leo Tolstoy's short story “Where Love Is, There God Is Alsoˮ (1885), its purpose is to substantiate the choice of the main source of the text for publication and to cleanse it of distortions. In the research literature, the issue of clarifying the history of formation of the given work as an artistic whole is open, details of the final stages of its creation have not been reconstructed, the editorship of this literary monument has not been concretized. The proposed work was performed in a certain sequence. First, all the discrepancies between the first lifetime editions of 1885–1886 were identified, and then a comparative analysis of them with handwritten materials was carried out. At the final stage, the classification of these discrepancies was correlated with the textual practice of the predecessors. As a result, the choice of the twelfth part of “The Works of Count L. N. Tolstoy” (1886) as the main text source for publication was theoretically justified, a list of recommended corrections based on manuscripts was compiled and argued. The tradition of criteria for scientific criticism of literary monuments has been supplemented with new principles. This is the transparency of editorial intrusions into someone else's text, the obligatory references to manuscripts or earlier publications in the list of corrections, a comprehensive disclosure of its composition (not a truncated format), the inadmissibility for a text critic to act as a co-author of the writer.

scholarly journals A NOVEL VLSI ARCHITECTURE OF HIGH SPEED 1D DISCRETE WAVELET TRANSFORM

2015 ◽  
pp. 160-166
Author(s):  
POOJA GUPTA ◽  
Saroj Kumar Lenka
Keyword(s):  
High Speed ◽  
Performance Metrics ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Fir Filter ◽  
Optimization Techniques ◽  
Discrete Wavelet ◽  
Path Delay ◽  
Linear Phase ◽  
Data Interleaving

This paper describes an efficient implementation for a multi-level convolution based 1-D DWT hardware architecture for use in FPGAs. The proposed architecture combines some hardware optimization techniques to develop a novel DWT architecture that has high performance and is suitable for portable and high speed devices. The first step towards the hardware implementation of the DWT algorithm was to choose the type of FIR filter block. Firstly we design the high speed linear phase FIR filter using pipelined and parallel arithmetic methods. This proposed filter employs efficiently distributed D-latches and multipliers. Furthermore this filter is used in the proposed DWT architecture. Thus, the new VLSI architecture based on combining of fast FIR filters for reducing the critical path delay and data interleaving technique for lower chip area. We synthesized the final design using Xilinx 9.1i ISE tool. We illustrate that a DWT design using a pipelined linear phase FIR filter coupled with data-interleaving gives the best combination of the performance metrics when compared to other DWT structures.

scholarly journals Low Power 32 x 32 – bit Reversible Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 852-856
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Reversible Logic ◽  
Low Power Consumption ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
X 32

Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

scholarly journals Comparative Analysis of High Speed Carry Skip Adders

2018 ◽  
Vol 7 (2.24) ◽  
pp. 121
Author(s):  
Ch Naga Babu ◽  
P Naga Siva Sai ◽  
Ch Priyanka ◽  
K Hari Kishore ◽  
M Bindu Bhargavi ◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Power Consumption ◽  
High Speed ◽  
Critical Path ◽  
Path Delay ◽  
Reduce Power Consumption ◽  
Hybrid Variable ◽  
Critical Path Delay ◽  
Variable Latency ◽  
Carry Skip Adders

In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed  a another method called Kogge-Stone adder here so it reduces the critical path delay. In Kogge-stone adder power is highly consumed due to more no of wiring connections so another adder was designed to reduce power consumption which is Sklansky adder which reduces power Consumption. This is done in Xilinx ISE 14.7 and power was analyzed using Xilinx power analyzer. 

scholarly journals Design and Implementation of Reversible Vedic Multiplier with Trlic

2020 ◽  
Vol 8 (6) ◽  
pp. 1530-1534
Keyword(s):  
Embedded System ◽  
Power Dissipation ◽  
High Speed ◽  
Mathematical Problem ◽  
Processing Application ◽  
Vedic Mathematics ◽  
Programmable Filter ◽  
Vedic Multiplier ◽  
Rules And Principles ◽  
Fixed Input

The 'Vedic Mathematics' is the name given to the ancient system of mathematics with a unique technique of calculations based on simple rules and principles with which any mathematical problem can be solved with the help of arithmetic, algebra, geometry or trigonometry. In any of the fastest ALU, multiplier play an inevitable role. There is always a demand on high speed multiplier due to the raising limitation on delay. Increasing the speed of a multiplier there are number of new techniques have been implemented in which multiplier using Vedic mathematics are foremost one. The system performance and delay depend on the performance of multiplier used in it. Multiplier are used in different area such as cryptography, image processing application, embedded system application, programmable filter application etc .One of the major techniques to scale back the power dissipation is Reversible logic. There is no loss of data therefore power dissipation is reduced producing distinctive output for fixed input and vice-versa. The main objective of the project is to scale back the TRLIC of the multiplier factor by exploitation of Vedic arithmetic.The proposed methods are designed using VHDL Programming language, simulation and synthesis are done using Cadence RTL compiler in 180nm technology.

scholarly journals VLSI Architecture of High Performance Multiplier for High Speed Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 442-445
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Full Adder ◽  
Vital Role ◽  
Path Delay

In the application of digital signal process multipliers play a vital role. With advances in technology, several researchers have tried and try to design multipliers which supply high speed, low power consumption, regularity of layout and thus less space or maybe combination of them in one multiplier factor. Thus, Compact VLSI design for four bit multiplier factor is planned during this paper that is appropriate for low power and high speed applications. Multiplier factor with high performance is achieved through the novel style of hybrid single bit full adder and Dadda algorithmic rule. The important path delay and power consumption of the planned multiplier factor square measure reduced by 65.9% and 24.5% severally when put next with existing multipliers. The planned multiplier factor is synthesized exploitation CADENCE five.1.0 EDA tool and simulated exploitation spectre virtuoso.

scholarly journals VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics

2015 ◽  
Vol 5 (2) ◽  
Author(s):  
Bharatha K. Babu ◽  
G. Nanthini
Keyword(s):  
Fourier Transform ◽  
Small Area ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Path Delay ◽  
Vedic Mathematics ◽  
Fft Processor ◽  
Wide Range ◽  
Single Path

Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FFT

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