scholarly journals Design and Implementation of Reversible Vedic Multiplier with Trlic

2020 ◽  
Vol 8 (6) ◽  
pp. 1530-1534
Keyword(s):  
Embedded System ◽  
Power Dissipation ◽  
High Speed ◽  
Mathematical Problem ◽  
Processing Application ◽  
Vedic Mathematics ◽  
Programmable Filter ◽  
Vedic Multiplier ◽  
Rules And Principles ◽  
Fixed Input

The 'Vedic Mathematics' is the name given to the ancient system of mathematics with a unique technique of calculations based on simple rules and principles with which any mathematical problem can be solved with the help of arithmetic, algebra, geometry or trigonometry. In any of the fastest ALU, multiplier play an inevitable role. There is always a demand on high speed multiplier due to the raising limitation on delay. Increasing the speed of a multiplier there are number of new techniques have been implemented in which multiplier using Vedic mathematics are foremost one. The system performance and delay depend on the performance of multiplier used in it. Multiplier are used in different area such as cryptography, image processing application, embedded system application, programmable filter application etc .One of the major techniques to scale back the power dissipation is Reversible logic. There is no loss of data therefore power dissipation is reduced producing distinctive output for fixed input and vice-versa. The main objective of the project is to scale back the TRLIC of the multiplier factor by exploitation of Vedic arithmetic.The proposed methods are designed using VHDL Programming language, simulation and synthesis are done using Cadence RTL compiler in 180nm technology.

A new design of a low-power reversible Vedic multiplier

2020 ◽  
Vol 18 (03) ◽  
pp. 2050002
Author(s):  
Meysam Rashno ◽  
Majid Haghparast ◽  
Mohammad Mosleh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Reversible Logic ◽  
Arithmetic Circuits ◽  
Quantum Cost ◽  
Computing Systems ◽  
Vedic Multiplier ◽  
Wide Range ◽  
Logic Unit

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

VLSI Implementation of High Speed Energy-Efficient Truncated Multiplier

2018 ◽  
Vol 27 (05) ◽  
pp. 1850077 ◽  
Author(s):  
K. N. Vijeyakumar ◽  
S. Elango ◽  
S. Kalaiselvi
Keyword(s):  
Power Dissipation ◽  
Energy Efficient ◽  
High Speed ◽  
Total Error ◽  
Absolute Error ◽  
Structural Level ◽  
Chip Area ◽  
Vedic Mathematics ◽  
Power Delay Product ◽  
Compiler Performance

In this brief, we present the design and evaluation of a high speed and energy-efficient truncated multiplier for unsigned multiplication, such that the average absolute error due to truncation and rounding is kept minimal. The proposed algorithm eliminates a few least significant Partial Product (PP) bits and adds correction bias at appropriate PP bit positions to minimize the total error. From the literatures reviewed, it is clear that there is scope for reducing delay in multiplication using sutras of ancient vedic mathematics. This work uses a simple “crosswise and vertical sutra” of Vedic mathematics to generate PP bits. The proposed methodology groups the input into [Formula: see text]/2 bits, eliminates least subgroup multiplication ([Formula: see text]) and deletes few least significant bits in other subgroup multiplications to reduce area and power dissipation. In addition, correction biase are added at appropriate bit positions to reduce the overall absolute error due to the elimination of few PP bits and rounding of final product. Experimental evaluation of the proposed truncated design is carried out through structural level VHDL modeling and simulations using Synopsys design compiler. Performance analysis revealed Chip-Area Ratio (CAR%) to be 33.81% and Power-Delay Product (PDP) of 14.84[Formula: see text]pJ of proposed truncated design for an [Formula: see text] multiplication.

scholarly journals Low Power 32 x 32 – bit Reversible Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 852-856
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Reversible Logic ◽  
Low Power Consumption ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
X 32

Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

scholarly journals Reversible Vedic Multiplier

2019 ◽  
Vol 8 (6S2) ◽  
pp. 852-857
Keyword(s):  
Embedded System ◽  
High Speed ◽  
Digital Signal ◽  
Design Parameters ◽  
Design Constraint ◽  
Performance Constraints ◽  
Multiplication Operation ◽  
Vedic Multiplier ◽  
Essential Components ◽  
Almost All

In the new era of technology speed effective advanced multiplier has greatest demand, where they acts as an essential part in almost all high speed processing units which are used currently. As the multiplier is one of the essential components in several computing machines, for instant microprocessors, DSPs (Digital Signal Processors) and quantum computational and combinational systems. The performances of different processors is measured based on number of multiplication completed per second. So efficient multiplier designs are to be found to meet these performance constraints and one such approach which provides solution to above problem is Vedic multiplier. It is simple in structure and increase the efficiency by reducing the unnecessary steps in multiplication. Furthermore, implementing the designed multiplier using reversible gates can decreases the dissipation of power also, which is another essential design constraint that to be met in an embedded system. In the present work, a 4X4 reversible Vedic multiplier is designed; moreover it can offers more efficiency in terms of reversible design parameters such as TRLIC (Total Reversible Logic Implementation Cost) and delay. Code for 4X4 Vedic multiplication operation is written using Verilog HDL programming language and simulation is done using Xilinx 14.7 ISE is targeted to selected FPGA device family as Vertex 6

scholarly journals Vedic Multiplier Implementation for High Speed Factorial Computation

2012 ◽  
Vol 1 (04) ◽  
pp. 01-06
Author(s):  
Prof. Sharayu Waghmare
Keyword(s):  
Comparative Analysis ◽  
High Speed ◽  
Vlsi Architecture ◽  
Path Delay ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
The Given ◽  
Mathematical Operations ◽  
Indian Mathematics

Vedic Mathematics arise from the prehistoric classification of Indian mathematics that was recreated by Tirthaji. Ancient mathematical operations are depending on sixteen methods. In this article, a new VLSI architecture to compute factorial of the given number with Vedic based multiplier is proposed. Simulations are performed using Xilinx ISE 14.2. Effective comparative analysis is made with existing multipliers to prove the momentous development in competence and high speed operation. This efficient multiplier is implemented in the proposed factorial architecture which significantly reduces the path delay and provides better optimization.

DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS

2014 ◽  
Vol 23 (07) ◽  
pp. 1450092 ◽  
Author(s):  
PRABIR SAHA ◽  
DEEPAK KUMAR ◽  
PARTHA BHATTACHARYYA ◽  
ANUP DANDAPAT
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Boolean Logic ◽  
Dynamic Power ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
Layout Area ◽  
And Performance

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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