scholarly journals Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

2011 ◽  
Vol 12 (5) ◽  
pp. 175-188 ◽  
Author(s):  
Yong-Bin Kim
Keyword(s):  
Carbon Nanotube ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Integrated Circuit Design ◽  
Effect Transistor

Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design

2021 ◽  
Vol 2021 (HiTEC) ◽  
pp. 000118-000122
Author(s):  
S. Perez ◽  
A.M. Francis ◽  
J. Holmes ◽  
T. Vrotsos
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Extreme Environment ◽  
Integrated Circuit Design ◽  
Device Model ◽  
Effect Transistor ◽  
R Process

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

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