Materials and Processes for Schottky Contacts on Silicon Carbide

Silicon carbide (4H-SiC) Schottky diodes have reached a mature level of technology and are today essential elements in many applications of power electronics. In this context, the study of Schottky barriers on 4H-SiC is of primary importance, since a deeper understanding of the metal/4H-SiC interface is the prerequisite to improving the electrical properties of these devices. To this aim, over the last three decades, many efforts have been devoted to developing the technology for 4H-SiC-based Schottky diodes. In this review paper, after a brief introduction to the fundamental properties and electrical characterization of metal/4H-SiC Schottky barriers, an overview of the best-established materials and processing for the fabrication of Schottky contacts to 4H-SiC is given. Afterwards, besides the consolidated approaches, a variety of nonconventional methods proposed in literature to control the Schottky barrier properties for specific applications is presented. Besides the possibility of gaining insight into the physical characteristics of the Schottky contact, this subject is of particular interest for the device makers, in order to develop a new class of Schottky diodes with superior characteristics.

Space charge capacitance study of GaP/Si multilayer structure grown by plasma deposition

Microcrystalline GaP/Si multilayer structures grown on GaP substrates using combination of PE-ALD for GaP and PECVD for Si layers deposition are studied by three main space charge capacitance techniques: C-V profiling, admittance spectroscopy (AS) and deep level transient spectroscopy (DLTS), which have been used on Schottky barriers formed on the GaP/Si multilayer structures. C-V profiling qualitatively demonstrates an electron accumulation in the Si/GaP wells. However, quantitative determination of the concentration and spatial position of its maximum is limited by the strong frequency dependence of the capacitance caused by electron capture/emission processes in/from the Si/GaP wells. These processes lead to signatures in AS and DLTS with activation energies equal to 0.39±0.05 eV and 0.28±0.05 eV, respectively, that are linked to the energy barrier at the GaP/Si interface. It is shown that the value obtained by AS (0.39±0.05 eV) is related to the response from Si/GaP wells located in the quasi-neutral region of the Schottky barrier, and it corresponds to the conduction band offset at the GaP/Si interface, while DLTS rather probes wells located in the space charge region closer to the Schottky interface where the internal electric field yields to a lowering of the effective barrier in the Si/GaP wells. Two additional signatures were detected by DLTS, which are identified as defect levels in GaP. The first one is associated to the SiGa+VP complex, while the second was already detected in single microcrystalline GaP layers grown by PE-ALD.

Unraveling the origin of ferroelectric resistance switching through the interfacial engineering of layered ferroelectric-metal junctions

Ferroelectric memristors have found extensive applications as a type of nonvolatile resistance switching memories in information storage, neuromorphic computing, and image recognition. Their resistance switching mechanisms are phenomenally postulated as the modulation of carrier transport by polarization control over Schottky barriers. However, for over a decade, obtaining direct, comprehensive experimental evidence has remained scarce. Here, we report an approach to experimentally demonstrate the origin of ferroelectric resistance switching using planar van der Waals ferroelectric α-In2Se3 memristors. Through rational interfacial engineering, their initial Schottky barrier heights and polarization screening charges at both terminals can be delicately manipulated. This enables us to find that ferroelectric resistance switching is determined by three independent variables: ferroelectric polarization, Schottky barrier variation, and initial barrier height, as opposed to the generally reported explanation. Inspired by these findings, we demonstrate volatile and nonvolatile ferroelectric memristors with large on/off ratios above 104. Our work can be extended to other planar long-channel and vertical ultrashort-channel ferroelectric memristors to reveal their ferroelectric resistance switching regimes and improve their performances.

Work function of polytypic gallium phosphide nanowires

In this work we investigate the work function of gallium phosphide nanowires by the means of frequency-modulated Kelvin probe force microscopy. Polytypic wurtzite/zinc blende nanowires were synthesized via self-catalytic molecular beam epitaxy. Mixed crystal phase was achieved by controlling the catalytic droplet contact angle and confirmed via transmission electron microscopy and Raman spectroscopy. Kelvin probe study showed a contrast between the work function of (110) zinc blende and (1120) wurtzite gallium phosphide: ϕZB = 4.28 eV and ϕWZ = 4.2 eV. Also, it was shown that sub-monolayer arsenic shell increases the work function up to 4.75 eV. Thus, two mechanisms for work function adjustment in the range 4.2-4.75 eV are shown. The results are important for optimization of Schottky barriers in nanowire-based devices.

Compact Modeling of Non-Linear Contact Effects in Short-Channel Coplanar and Staggered Organic Thin-Film Transistors

<div>We present analytical physics-based compact models for the Schottky barriers at the interfaces between the organic semiconductor and the source and drain contacts in organic thin-film transistors (TFTs) fabricated in the coplanar and the staggered device architecture, and we illustrate the effect of these Schottky barriers on the current-voltage characteristics of the TFTs. The model for the source barrier explicitly takes into account the field-dependent barrier lowering due to image charges. Potential solutions have been derived by applying the Schwarz-Christoffel transformation, leading to expressions for the electric field at the source barrier and for the contact resistance at the source contact. With regard to the drain barrier, a generic compact-modeling scheme based on the current-voltage characteristics of a barrier-less TFT is introduced that can be applied to any compact dc model. Finally, both models are incorporated into an existing charge-based compact dc model and verified against the results of measurements performed on coplanar and staggered organic TFTs with channel lengths ranging from 0.5 μm to 10.5 μm.</div>