Signal Transmission Properties Improvement of Serial Advanced Technology Attachment Connector Using Analysis of Differential Impedance

Author(s):  
Jeong-Kyu Yang ◽  
Moonjung Kim
2021 ◽  
Vol 9 ◽  
Author(s):  
Lauryn Benedict ◽  
Braelei Hardt ◽  
Lorraine Dargis

To function effectively, animal signals must transmit through the environment to receivers, and signal transmission properties depend on signal form. Here we investigated how the transmission of multiple parts of a well-studied signal, bird song, varies between males and females of one species. We hypothesized that male and female songs would have different transmission properties, reflecting known differences in song form and function. We further hypothesized that two parts of male song used differentially in broadcast singing and aggressive contests would transmit differently. Analyses included male and female songs from 20 pairs of canyon wrens (Catherpes mexicanus) played and re-recorded in species-typical habitat. We found that male song cascades used in broadcast singing propagated farther than female songs, with higher signal-to-noise ratios at distance. In contrast, we demonstrated relatively restricted propagation of the two vocalization types typically used in short-distance aggressive signaling, female songs and male “cheet” notes. Of the three tested signals, male “cheet” notes had the shortest modeled propagation distances. Male and female signals blurred similarly, with variable patterns of excess attenuation. Both male song parts showed more consistent transmission across the duration of the signal than did female songs. Song transmission, thus, varied by sex and reflected signal form and use context. Results support the idea that males and females of the same species can show distinctly different signal evolution trajectories. Sexual and social selection pressures can shape sex-specific signal transmission, even when males and females are communicating in shared physical environments.


Author(s):  
Chandrashekhar V. Patil ◽  
Suma M. S

Abstract The conventional methods for testing the Dual Port Random Access Memories (DPRAM) may not be suitable for the Three-Dimensional Integrated Circuit (3-D IC) structures, due to their limited test vectors with heterogeneous integration. This paper takes an Application Specific Integrated Chips (ASIC) approach to gain some insight into the Front-end behavioral testing and backend routability of the dual port memories with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3-D IC structure. The presented implementation used commercially available Dual Port memories from the two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI), which is based on the SATA 2.6 AHCI host and external SATA (eSATA) standard bus architecture, with My_foundry’s 14nm low power process (14lp) technologies for the logical and physical implementations. The methodology evaluates the memory quality and performance/characteristics, in terms of timing, power and area. This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment.


2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Yu Lu ◽  
Wei Wu ◽  
Ke-yi Wang

This paper presents the implementation aspects and design of high-speed data transmission in laser direct-writing lithography. With a single field programmable gate array (FPGA) chip, mass data storage management, transmission, and synchronization of each part in real-time were implemented. To store a massive amount of data and transmit data with high bandwidth, a serial advanced technology attachment (SATA) intellectual property (IP) was developed on Xilinx Virtex-6 FPGA. In addition, control of laser beam power, collection of status read back data of the lithography laser through an analog-to-digital converter, and synchronization of the positioning signal were implemented on the same FPGA. A data structure for each unit with a unique exposure dose and other necessary information was established. Results showed that the maximum read bandwidth (240 MB/s) and maximum write bandwidth (200 MB/s) of a single solid-state drive conform to the data transmission requirement. The total amount of data meets the requirement of a large-area diffractive element approximately 102 cm2. The throughput has been greatly improved at meters per second or square centimeter per second. And test results showed that data transmission meets the requirement of the experiment.


2015 ◽  
Vol 2015 ◽  
pp. 1-13
Author(s):  
Takashi Kawamoto ◽  
Masato Suzuki ◽  
Takayuki Noto

A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 μs to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 μm CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 μm and 18 mW, respectively.


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