scholarly journals High-Speed Transmission and Mass Data Storage Solutions for Large-Area and Arbitrarily Structured Fabrication through Maskless Lithography

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Yu Lu ◽  
Wei Wu ◽  
Ke-yi Wang
Keyword(s):  
Data Storage ◽  
Data Transmission ◽  
High Speed ◽  
Exposure Dose ◽  
Advanced Technology ◽  
Beam Power ◽  
Direct Writing ◽  
Large Area ◽  
Mass Data ◽  
Serial Advanced Technology Attachment

This paper presents the implementation aspects and design of high-speed data transmission in laser direct-writing lithography. With a single field programmable gate array (FPGA) chip, mass data storage management, transmission, and synchronization of each part in real-time were implemented. To store a massive amount of data and transmit data with high bandwidth, a serial advanced technology attachment (SATA) intellectual property (IP) was developed on Xilinx Virtex-6 FPGA. In addition, control of laser beam power, collection of status read back data of the lithography laser through an analog-to-digital converter, and synchronization of the positioning signal were implemented on the same FPGA. A data structure for each unit with a unique exposure dose and other necessary information was established. Results showed that the maximum read bandwidth (240 MB/s) and maximum write bandwidth (200 MB/s) of a single solid-state drive conform to the data transmission requirement. The total amount of data meets the requirement of a large-area diffractive element approximately 102 cm2. The throughput has been greatly improved at meters per second or square centimeter per second. And test results showed that data transmission meets the requirement of the experiment.

Design and Implementation of General High-Speed Data Storage System

2014 ◽  
Vol 989-994 ◽  
pp. 2414-2417
Author(s):  
Gang Fu ◽  
Wen Jian Geng ◽  
Ren Long Li
Keyword(s):  
Computer System ◽  
Data Storage ◽  
Data Transmission ◽  
High Speed ◽  
Storage System ◽  
Time Data ◽  
Array Storage ◽  
Data Storage System ◽  
High Speed Data ◽  
The One

According to the trend of the development of the computer system bus more, designs the general high-speed data storage system based on computer platform structure.Put forward the "one-way chain" cache structure, to avoid the computer operating system of real-time data transmission, the influence of the multithreaded mode data transmission and storage of parallel processing.According to the basic principle of data storage in a computer system, put forward the standard file operations function replace special instruction set, the method of implementing the SCSI disk array storage at a high speed.Test results show that the data storage system based on computer platform with more generalization method to achieve the high speed of data storage.

High-Speed, Large-Area POF Receivers for Fiber Characterization and Data Transmission $\geq$10-Gb/s Based on MSM-Photodetectors

2013 ◽  
Vol 31 (7) ◽  
pp. 1132-1137 ◽  
Author(s):  
Sven Loquai ◽  
Florian Winkler ◽  
Stefan Wabra ◽  
Engelbert Hartl ◽  
Bernhard Schmauss ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Large Area ◽  
Msm Photodetectors ◽  
Fiber Characterization

Analysis of Inter-Satellite Optical Wireless Communication System

2017 ◽  
Vol 7 (10) ◽  
pp. 10
Author(s):  
Rajbir Singh
Keyword(s):  
Wireless Communication ◽  
Optical Networks ◽  
Data Transmission ◽  
High Speed ◽  
Open Space ◽  
Communication Link ◽  
Optical Wireless Communication ◽  
Optical Wireless ◽  
High Speed Data ◽  
Speed Data Transmission

Optical networks are bandwidth efficient networks are used for long haul communication providing seamless data transfer. For high speed data transmission in open space between different satellites, Inter-satellite Optical wireless communication (IsOWC) is widely used .In this paper we have evaluated the performance of IsOWC communication link for high speed data transmission .The performance of the system is evaluated on the basis of qualitative parameters such as Q-factor and BER using optisystem simulator.

Top-down Fabricated Gold Nanostrip on Silicon-on-insulator Wafer: A Promising Building Block towards Ultra-compact Optical Device

Nanoscale ◽  
2020 ◽  
Author(s):  
Fuping Zhang ◽  
Weikang Liu ◽  
Li Chen ◽  
Zhiqiang Guan ◽  
Hongxing Xu
Keyword(s):  
Optical Communication ◽  
Data Transmission ◽  
Building Block ◽  
High Speed ◽  
Large Data ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Fundamental Building Block ◽  
Low Energy Consumption ◽  
Controllable Fabrication

he plasmonic waveguide is the fundamental building block for high speed, large data transmission capacity, low energy consumption optical communication and sensing. Controllable fabrication and simultaneously optimization of the propagation...

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

A Dicode Signaling Scheme for Capacitively Coupled Interface

2011 ◽  
Vol 497 ◽  
pp. 296-305
Author(s):  
Yasushi Yuminaka ◽  
Kyohei Kawano
Keyword(s):  
Partial Response ◽  
Data Transmission ◽  
High Speed ◽  
Circuit Simulation ◽  
Frequency Bandwidth ◽  
Capacitively Coupled ◽  
Limited Frequency ◽  
Simulation Results ◽  
Response Coding ◽  
The Impact

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.

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