All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

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RiSA: A Reinforced Systolic Array for Depthwise Convolutions and Embedded Tensor Reshaping

ACM Transactions on Embedded Computing Systems ◽

10.1145/3476984 ◽

2021 ◽

Vol 20 (5s) ◽

pp. 1-20

Author(s):

Hyungmin Cho

Keyword(s):

Neural Networks ◽

Convolutional Neural Networks ◽

Language Processing ◽

Systolic Array ◽

Data Reuse ◽

Systolic Arrays ◽

High Data ◽

Area Efficiency ◽

High Area ◽

Accelerator Design

Depthwise convolutions are widely used in convolutional neural networks (CNNs) targeting mobile and embedded systems. Depthwise convolution layers reduce the computation loads and the number of parameters compared to the conventional convolution layers. Many deep neural network (DNN) accelerators adopt an architecture that exploits the high data-reuse factor of DNN computations, such as a systolic array. However, depthwise convolutions have low data-reuse factor and under-utilize the processing elements (PEs) in systolic arrays. In this paper, we present a DNN accelerator design called RiSA, which provides a novel mechanism that boosts the PE utilization for depthwise convolutions on a systolic array with minimal overheads. In addition, the PEs in systolic arrays can be efficiently used only if the data items ( tensors ) are arranged in the desired layout. Typical DNN accelerators provide various types of PE interconnects or additional modules to flexibly rearrange the data items and manage data movements during DNN computations. RiSA provides a lightweight set of tensor management tasks within the PE array itself that eliminates the need for an additional module for tensor reshaping tasks. Using this embedded tensor reshaping, RiSA supports various DNN models, including convolutional neural networks and natural language processing models while maintaining a high area efficiency. Compared to Eyeriss v2, RiSA improves the area and energy efficiency for MobileNet-V1 inference by 1.91× and 1.31×, respectively.

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A floating high-voltage level-shifter with high area efficiency for biomedical implants

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) ◽

10.1109/prime.2016.7519451 ◽

2016 ◽

Cited By ~ 1

Author(s):

Michael Haas ◽

Maurits Ortmanns

Keyword(s):

High Voltage ◽

Biomedical Implants ◽

Voltage Level ◽

Area Efficiency ◽

High Area ◽

Level Shifter

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An Electrostatic Discharge Protection Circuit Technique for the Mitigation of Single-Event Transients in SiGe BiCMOS Technology

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2017.2778946 ◽

2018 ◽

Vol 65 (1) ◽

pp. 426-431 ◽

Cited By ~ 2

Author(s):

Moon-Kyu Cho ◽

Ickhyun Song ◽

Spyridon Pavlidis ◽

Zachary E. Fleetwood ◽

Stephen P. Buchner ◽

...

Keyword(s):

Electrostatic Discharge ◽

Single Event ◽

Single Event Transients ◽

Bicmos Technology ◽

Sige Bicmos ◽

Protection Circuit ◽

Circuit Technique

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A scalable ASIP for BP Polar decoding with multiple code lengths

MATEC Web of Conferences ◽

10.1051/matecconf/201823201046 ◽

2018 ◽

Vol 232 ◽

pp. 01046

Author(s):

Wan Qiao ◽

Dake Liu

Keyword(s):

Cmos Technology ◽

Single Instruction Multiple Data ◽

Instruction Set ◽

Maximum Throughput ◽

Specific Instruction ◽

Area Efficiency ◽

Multiple Data ◽

High Area ◽

Multiple Code ◽

Application Specific

In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.

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