Density of states of short channel amorphous In–Ga–Zn–O thin-film transistor arrays fabricated using manufacturable processes

2015 ◽  
Vol 54 (5) ◽  
pp. 051101 ◽  
Author(s):  
Soo Chang Kim ◽  
Young Sun Kim ◽  
Jerzy Kanicki
2009 ◽  
Vol 48 (3) ◽  
pp. 03B020 ◽  
Author(s):  
Ki-Cheol Cheon ◽  
Juhyun Woo ◽  
Deuk-Soo Jung ◽  
Mungi Park ◽  
Hwan Kim ◽  
...  

Materials ◽  
2019 ◽  
Vol 12 (11) ◽  
pp. 1739 ◽  
Author(s):  
Kyungsoo Jang ◽  
Youngkuk Kim ◽  
Joonghyun Park ◽  
Junsin Yi

We investigated the characteristics of excimer laser-annealed polycrystalline silicon–germanium (poly-Si1−xGex) thin film and thin-film transistor (TFT). The Ge concentration was increased from 0% to 12.3% using a SiH4 and GeH4 gas mixture, and a Si1−xGex thin film was crystallized using different excimer laser densities. We found that the optimum energy density to obtain maximum grain size depends on the Ge content in the poly-Si1−xGex thin film; we also confirmed that the grain size of the poly-Si1−xGex thin film is more sensitive to energy density than the poly-Si thin film. The maximum grain size of the poly-Si1−xGex film was 387.3 nm for a Ge content of 5.1% at the energy density of 420 mJ/cm2. Poly-Si1−xGex TFT with different Ge concentrations was fabricated, and their structural characteristics were analyzed using Raman spectroscopy and atomic force microscopy. The results showed that, as the Ge concentration increased, the electrical characteristics, such as on current and sub-threshold swing, were deteriorated. The electrical characteristics were simulated by varying the density of states in the poly-Si1−xGex. From this density of states (DOS), the defect state distribution connected with Ge concentration could be identified and used as the basic starting point for further analyses of the poly-Si1−xGex TFTs.


1998 ◽  
Vol 09 (03) ◽  
pp. 703-723 ◽  
Author(s):  
BENJAMIN IÑIGUEZ ◽  
TOR A. FJELDLY ◽  
MICHAEL S. SHUR

We review recent physics-based, analytical DC models for amorphous silicon (a-Si), polysilicon (poly-Si), and organic thin film transistors (TFTs), developed for the design of novel ultra high-resolution, large area displays using advanced short-channel TFTs. In particular, we emphasize the modeling issues related to the main short-channel effects, such as self-heating (a-Si TFTs) and kink effect (a-Si and poly-Si TFTs), which are present in modern TFTs. The models have been proved to accurately reproduce the DC characteristics of a-Si:H with gate lengths down to 4 μm and poly-Si TFTs with gate lengths down to 2 μm. Because the scalability of the models and the use of continuous expressions for describing the characteristics in all operating regimes, the models are suitable for implementation in circuit simulators such as SPICE.


2006 ◽  
Vol 37 (1) ◽  
pp. 254 ◽  
Author(s):  
J. H. Park ◽  
W. J. Nam ◽  
J. H. Lee ◽  
M. K. Han ◽  
K. Y. Lee ◽  
...  

2014 ◽  
Vol 74 ◽  
pp. 11-18 ◽  
Author(s):  
Xingwei Ding ◽  
He Ding ◽  
Chuanxin Huang ◽  
Hao Zhang ◽  
Weimin Shi ◽  
...  

Author(s):  
Youssef Ahmed Mobarak ◽  
Moamen Atef

<span>The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La<sub>2</sub>O<sub>3</sub>K<sub>ox</sub>=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO<sub>2</sub>K<sub>sp</sub>=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.</span>


AIP Advances ◽  
2015 ◽  
Vol 5 (4) ◽  
pp. 047123 ◽  
Author(s):  
Long Wang ◽  
Nianduan Lu ◽  
Ling Li ◽  
Zhuoyu Ji ◽  
Writam Banerjee ◽  
...  

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