Fabrication of Short-Channel Thin-Film Transistor Using Conventional Photolithography

2009 ◽  
Vol 48 (3) ◽  
pp. 03B020 ◽  
Author(s):  
Ki-Cheol Cheon ◽  
Juhyun Woo ◽  
Deuk-Soo Jung ◽  
Mungi Park ◽  
Hwan Kim ◽  
...  
1998 ◽  
Vol 09 (03) ◽  
pp. 703-723 ◽  
Author(s):  
BENJAMIN IÑIGUEZ ◽  
TOR A. FJELDLY ◽  
MICHAEL S. SHUR

We review recent physics-based, analytical DC models for amorphous silicon (a-Si), polysilicon (poly-Si), and organic thin film transistors (TFTs), developed for the design of novel ultra high-resolution, large area displays using advanced short-channel TFTs. In particular, we emphasize the modeling issues related to the main short-channel effects, such as self-heating (a-Si TFTs) and kink effect (a-Si and poly-Si TFTs), which are present in modern TFTs. The models have been proved to accurately reproduce the DC characteristics of a-Si:H with gate lengths down to 4 μm and poly-Si TFTs with gate lengths down to 2 μm. Because the scalability of the models and the use of continuous expressions for describing the characteristics in all operating regimes, the models are suitable for implementation in circuit simulators such as SPICE.


2006 ◽  
Vol 37 (1) ◽  
pp. 254 ◽  
Author(s):  
J. H. Park ◽  
W. J. Nam ◽  
J. H. Lee ◽  
M. K. Han ◽  
K. Y. Lee ◽  
...  

Author(s):  
Youssef Ahmed Mobarak ◽  
Moamen Atef

<span>The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La<sub>2</sub>O<sub>3</sub>K<sub>ox</sub>=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO<sub>2</sub>K<sub>sp</sub>=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.</span>


1994 ◽  
Vol 345 ◽  
Author(s):  
Kola R Olasupo ◽  
Professor M. K. Hatalis

AbstractThe polysilicon thin film transistor has been actively studied for the large area display applications like active matrix liquid crystal displays and for load cell in static random access memories. Due to low effective carrier mobility in polysilicon, the circuit speed is limited. Since the circuit delay time is directly proportional to the square of the channel length, short channel TFTs will be advantageous for high speed applications. In this work, we have studied the current voltage characteristics of an inverted sub-micron P-channel polysilicon thin-film transistor with self-aligned LDD structure to obtain a well-controlled channel and drain offset lengths. The particular features we examined are the leakage current and mobility. The leakage current and the ON current were found to be in the picoamp and micro-amp range respectively for devices having channel length in the range of 1.0μm to 0.35μm. Even very small devices having L&W = 0.35μm × 0.35μm exhibited characteristics similar to wider devices. The on/off current ratio was in the order of 105 before hydrogenation.


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