Threshold-voltage bias-temperature instability in commercially-available SiC MOSFETs

2016 ◽  
Vol 55 (4S) ◽  
pp. 04EA03 ◽  
Author(s):  
Ron Green ◽  
Aivars Lelis ◽  
Daniel Habersat
2019 ◽  
Vol 963 ◽  
pp. 749-752
Author(s):  
Jose Ortiz Gonzalez ◽  
Olayiwola Alatise ◽  
Philip A. Mawby

The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.


Author(s):  
S Suvarna ◽  
K Rajesh ◽  
T Radhu

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.


Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 427 ◽  
Author(s):  
Alejandro Campos-Cruz ◽  
Guillermo Espinosa-Flores-Verdad ◽  
Alfonso Torres-Jacome ◽  
Esteban Tlelo-Cuautle

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.


2010 ◽  
Vol 31 (4) ◽  
pp. 287-289 ◽  
Author(s):  
Minseok Jo ◽  
Seonghyun Kim ◽  
Seungjae Jung ◽  
Ju-Bong Park ◽  
Joonmyoung Lee ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document