An Ultra-Low-Power STT-MRAM-Based Multi-Core Associative Coprocessor with Inter-Core Pipeline Scheme for Large-Scale Full-Adaptive Nearest Pattern Search

In an attempt to realize tiny "knowledge vehicles" called intelligent quantum (IQ) chips for use in the coming ubiquitous network society, this paper presents the present status and future prospects of ultra-small-size and ultra-low-power III-V quantum logic large scale integrated circuits based on a novel hexagonal binary-decision diagram (BDD) quantum circuit architecture. Here, quantum transport in path switching node devices formed on III-V semiconductor-based hexagonal nanowire networks is controlled by nanometer scale Schottky wrap gates (WPGs) to realize arbitrary combinational logic function. Feasibility of the approach is shown through fabrication of basic node devices and various small-scale circuits, and approaches for higher density integration and larger scale circuits are discussed.

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Measuring of an unknown voltage by using single electron transistor based voltmeter

Semiconductor Physics Quantum Electronics & Optoelectronics ◽

10.15407/spqeo24.03.277 ◽

2021 ◽

Vol 24 (3) ◽

pp. 277-287

Author(s):

A.K. Biswas ◽

Keyword(s):

Low Power ◽

Large Scale ◽

Low Noise ◽

Single Electron ◽

Single Electron Transistor ◽

Flip Flop ◽

Ultra Low Power ◽

Integration Density ◽

Single Electron Device ◽

Ultra Low Noise

In engineering and science, high operating speed, low power consumption, and high integration density equipment are financially indispensable. Single electron device (SED) is one such equipment. SEDs are capable of controlling the transport of only one electron through the tunneling transistor. It is single electron that is sufficient to store information in SED. Power consumed in the single electron circuit is very low in comparison with CMOS circuits. The processing speed of single electron transistor (SET) based device will be nearly close to electronic speed. SET attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences for the case of a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. For implementing a single electron transistor based voltmeter circuit, SET would be the best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling SEDs. A D Flip-Flop is implemented and based on this, two kinds of registers like sequence register and сode register are made.

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TOWARD ULTRA-LOW POWER III-V QUANTUM LARGE SCALE INTEGRATED CIRCUITS FOR UBIQUITOUS NETWORK ERA

Frontiers in Electronics ◽

10.1142/9789812773081_0025 ◽

2006 ◽

Author(s):

HIDEKI HASEGAWA ◽

SEIYA KASAI ◽

TAKETOMO SATO

Keyword(s):

Integrated Circuits ◽

Low Power ◽

Large Scale ◽

Ultra Low Power ◽

Ubiquitous Network ◽

Network Era

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Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea8040047 ◽

2018 ◽

Vol 8 (4) ◽

pp. 47 ◽

Cited By ~ 5

Author(s):

Jennifer Hasler ◽

Aishwarya Natarajan ◽

Sihwan Kim

Keyword(s):

Low Power ◽

Open Source ◽

Energy Efficient ◽

Large Scale ◽

System Level ◽

Physical Computing ◽

Ultra Low Power ◽

Mixed Signal ◽

Starting Point ◽

Analog Arrays

This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. Abstraction is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches.

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