Analysis of Intrinsic and Parasitic Gate Delay of InGaAs HEMTs

One of the main shortcomings in a field effect diode (FED) is its scaling. Use of an oxide layer in the channel is proposed to enhance the control of the gate on the channel carriers. This is the so-called silicon on raised insulator FED (SORI-FFD) structure. The Shockley–Read–Hall (SRH) mechanism is one of the main components of leakage current in FED devices. The potential induced by the gates in the OFF-state of a SORI-FFD, is larger than that induced by the gates of a regular FED. This reduces, SRH recombination rate. Hence, OFF-state characteristics of the SORI-FED device improves. We evaluate the impact of band-to-band tunneling (BTBT) on the electrical characteristics of Modified FED (M-FED).We show that for channel lengths of 35 nm and lower this device does not turn off. While, the proposed structure makes device channel length scaling possible down to 15 nm. We will also compare electrical characteristics of SORI-FED and M-FED using three metrics: gate delay time versus channel length, gate delay time versus I ON /I OFF ratio and energy-delay product versus channel length. Benchmarking results show the proposed FED structure provides improvement in I ON /I OFF ratio and holds promise for future logic transistor applications.

Download Full-text

Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials

VLSI Design ◽

10.1155/2018/9269157 ◽

2018 ◽

Vol 2018 ◽

pp. 1-7 ◽

Cited By ~ 3

Author(s):

Yin Li ◽

Yu Zhang ◽

Xiaoli Guo

Keyword(s):

Time Delay ◽

Special Class ◽

Time Complexity ◽

Space Complexity ◽

Polynomial Basis ◽

Gate Delay ◽

Complexity Bound ◽

Parallel Multiplier ◽

Highly Efficient ◽

First Time

Recently, we present a novel Mastrovito form of nonrecursive Karatsuba multiplier for all trinomials. Specifically, we found that related Mastrovito matrix is very simple for equally spaced trinomial (EST) combined with classic Karatsuba algorithm (KA), which leads to a highly efficient Karatsuba multiplier. In this paper, we consider a new special class of irreducible trinomial, namely, xm+xm/3+1. Based on a three-term KA and shifted polynomial basis (SPB), a novel bit-parallel multiplier is derived with better space and time complexity. As a main contribution, the proposed multiplier costs about 2/3 circuit gates of the fastest multipliers, while its time delay matches our former result. To the best of our knowledge, this is the first time that the space complexity bound is reached without increasing the gate delay.

Download Full-text

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept

2017 15th IEEE International New Circuits and Systems Conference (NEWCAS) ◽

10.1109/newcas.2017.8010166 ◽

2017 ◽

Cited By ~ 4

Author(s):

Assia El-Hadbi ◽

Abdelkarim Cherkaoui ◽

Oussama Elissati ◽

Jean Simatic ◽

Laurent Fesquet

Keyword(s):

Gate Delay ◽

Proof Of Concept

Download Full-text

Statistical Gate-Delay Modeling with Copulas

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v15i3.138 ◽

2020 ◽

Vol 15 (3) ◽

pp. 1-10

Author(s):

Walter Schneider

Keyword(s):

Circuit Design ◽

Integrated Circuit ◽

Process Variations ◽

Deep Submicron ◽

Experimental Results ◽

Gate Delay ◽

Integrated Circuit Design ◽

Circuit Performance ◽

Delay Models ◽

Innovative Concept

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

Download Full-text