scholarly journals Effects of cobalt deposition and pretreatment process on electrical properties of products

2021 ◽  
Author(s):  
Shaohui Xu ◽  
Haisheng Miao ◽  
Jiandong Zhang
Keyword(s):  
Electrical Properties ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Si Substrate ◽  
Access Memory ◽  
Bias Power ◽  
Optimal Value ◽  
Natural Oxide ◽  
Cobalt Deposition

Abstract The preferable conditions for formation of high quality CoSi2 films and effect of process parameters on properties of products were investigated. The pretreatment should not only remove the natural oxide layer completely, but also could not damage Si substrate. The good static random access memory (SRAM) proportion of products is high when pretreatment thickness is 20 Å, reached 96.5%. The radio frequency (RF) bias power process parameter should also take an optimal value. When RF bias power is 150 W, the good SRAM proportion of products is greater than 98%. The 100 Å Co can just completely react with Si substrate after twice annealing (500℃ 30s and 750℃ 30s), and if it exceeds 100 Å, Co will be residual. Decreasing Co thickness leads to contact resistance (RC) increase whatever in N-well or P-well. The overall standby current (Isb) of product is least when Co thickness is 80 Å. Finally, the products achieved good electrical properties when Co thickness is 80 Å, pretreatment thickness is 20 Å and RF bias power is 150 W.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Challenges and Benefits of Product-Like SRAM in Technology Development

2011 ◽  
Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  
Keyword(s):  
Technology Development ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Development Phase ◽  
High Complexity ◽  
Access Memory ◽  
Integration Schemes ◽  
Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

Effects of Thickness on Resistance Switching Properties of ZnMn2O4 Films Deposited by Magnetron Sputtering

2014 ◽  
Vol 941-944 ◽  
pp. 1275-1278
Author(s):  
Hua Wang ◽  
Zhi Da Li ◽  
Ji Wen Xu ◽  
Yu Pei Zhang ◽  
Ling Yang ◽  
...  
Keyword(s):  
Magnetron Sputtering ◽  
Random Access ◽  
Random Access Memory ◽  
Resistance Switching ◽  
Switching Behavior ◽  
Si Substrate ◽  
Access Memory ◽  
Resistive Switching Behavior ◽  
Bipolar Resistive Switching ◽  
Resistance Random Access Memory

ZnMn2O4films for resistance random access memory (RRAM) were fabricated on p-Si substrate by magnetron sputtering. The effects of thickness onI-Vcharacteristics, resistance switching behavior and endurance characteristics of ZnMn2O4films were investigated. The ZnMn2O4films with a structure of Ag/ZnMn2O4/p-Si exhibit bipolar resistive switching behavior. With the increase of thickness of ZnMn2O4films from 0.83μm to 2.3μm, both theVONand the number of stable repetition switching cycle increase, but theRHRS/RLRSratio decrease, which indicated that the ZnMn2O4films with a thickness of 0.83μm has the biggestRHRS/RLRSratio and the lowestVONandVOFF, but the worst endurance characteristics.

AS8‐static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

2017 ◽  
Vol 11 (1) ◽  
pp. 89-94 ◽  
Author(s):  
Ihsen Alouani ◽  
Wael M. Elsharkasy ◽  
Ahmed M. Eltawil ◽  
Fadi J. Kurdahi ◽  
Smail Niar
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Soft Error ◽  
Static Random Access Memory ◽  
Access Memory

scholarly journals Pitfall of the Strongest Cells in Static Random Access Memory Physical Unclonable Functions

Sensors ◽  
2018 ◽  
Vol 18 (6) ◽  
pp. 1776 ◽  
Author(s):  
Mingyang Gong ◽  
Hailong Liu ◽  
Run Min ◽  
Zhenglin Liu
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Physical Unclonable Functions

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

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