An investigation on function of current type on solder joint degradation in electronic packages

Purpose As in real applications several alternating current (AC) currents may be injected to the electronic devices, this study aims to analyze their effects on the lifetime of the solder joints and, consequently, shed the light on these effects at the design phase for other researchers to consider. Design/methodology/approach In this paper, the authors investigated on current waveform shapes on the performance and reliability of the solder joints in electronic package. Three common and extensively used current shapes in several simulations and experiments were selected to study their effects on the solder joint performance. Findings The results demonstrate a sever thermal swing and stress fluctuation in the solder joint induced in the case of triangle current type because the critical states lack any relaxation time. In fact, the stress intensification in the solder under application of the triangle current type has been shown to contribute to increasing brittle intermetallic compounds. An accelerated increase of on-state voltage of power semiconductor was also observed in under application of the triangle current type. Originality/value The originality of this paper is confirmed.

Experimental and finite element analysis on determining the fatigue life of pb-free solder joint (Sn-0.5Cu-3Bi-1Ag) used in electronic packages under harmonic loads

Electronic packages that are used these days are exposed to different types of vibration loadings in their usage environment. This vibration exposure can be categorized as harmonic and random vibrations. When reliability assessment of modern electronic systems is considered, vibration loading has an important role to play. One of the biggest challenges facing today is the accurate and rapid assessment of fatigue life under the vibration loading. Conventional solder joints were made of lead-tin alloy. According to many environment legislations and rules, lead is prohibited as an ingredient in the solder alloy. The reason for the prohibition of the usage of the lead is that it poisons the environment. In this study, Sn-0.5Cu-3Bi-1Ag is used as the lead-free solder alloy. Fatigue life prediction of electronic package containing SAC405 is conducted with the aid of vibration testing and Finite element analysis under harmonic vibration loading. A specially designed Plastic Ball Grid Array Package (PBGA) component is mounted on Printed Circuit Board (PCB). It is taken as a test vehicle for the vibration test. The test vehicle is excited by a sinusoidal vibration. The frequency of this excitation equals the fundamental frequency of the test vehicle and it is continued till the component fails. Since the solder balls are very small for direct measurement, Finite Element analysis (FEA) is used for noting down the stresses. The stress versus failures cycles (S-N) curve is made by relating both the stresses on the solder balls obtained and the number of failure cycles from vibration analysis. The fatigue life of the component can be estimated from the generated S-N curve. It is analyzed that the methodology is effective in predicting the component’s life. Hence, the reliability of electronic package can be improved.

A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

The relentless advancement and trends on thinner packages have become the focus in the semiconductor manufacturing industry. The requirement of thinner packages also demands a thinner vertical structure of the semiconductor electronic design. As a major contributor on the vertical structure of the electronic package, die or wafer is also essential to go thinner. As the wafer becomes thinner, various problems may occur during transport and even the backgrinding process itself. Wafer warpage is one of the main concerns during the wafer backgrinding process. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poor grinding and broken wafer. Wafer backgrinding stress and backgrinding tape tension also contribute to the effect on wafer warpage. Challenges exist in processing different silicon wafer technology, particularly the silicon-on-insulator (SOI) technology. Evaluating the effect of backgrinding tape selection and vacuum efficiency to eliminate such warpage is presented in this paper.