Motorsport Data Acquisition System and Live Telemetry using FPGA based CAN controller

The paper describes the design and working of a motorsport data acquisition, logging, live telemetry, and display system developed using the Controller Area Network (CAN) communication protocol as the backbone of the arrangement. The main controller of the CAN system is the myRIO which was programmed using LabVIEW. A Formula One car hosts over a hundred sensors during each of its races. The data acquisition/logging system, although does not directly affect the car’s performance, is indispensable when it comes to the testing and design phase of the car. Designers can validate their assumptions and calculations, real-time data during testing can be a safety indicator and it provides insight to the driver about the performance of the vehicle. The FPGA-based controller for CAN is designed for data acquisition and live telemetry system with the interest of the formula car team in mind. The design choices were made to improve and deliver a more effective system than the pre-existing ones. All choices of controllers, sensors, formatting were custom made for the requirements of the team. All programmable devices were coded individually to suit the system and the graphical user interface was designed internally. Data acquired by the proposed system helps in making sure that the car achieves the goals that were envisioned when it was designed.

Digital demodulators for analog signals: comparative analysis and simulation

The paper examines digital demodulators for two commonly used techniques of modulating analog signals: amplitude modulation (AM) and frequency modulation (FM). The described demodulators can be used to perform the radio monitoring of narrowband signal ranges including FM broadcasting stations as well as license-free CB, LPD, PMR bands. The demodulators considered in this work are intended for programmable devices with limited memory and computing resources, for example, for STM32F407 microcontrollers and similar ones. The paper presents the analysis and simulation of demodulators for AM signals, FM signals with low modulation indices and for FM signals without restriction on the modulation indices. In addition, the authors demonstrate how to demodulate the phase-modulation signal using a quadrature demodulator. The number of operations that are available for demodulation is limited by IF multiplication and filtering. The simulation of the analyzed demodulation algorithms was carried out in the Scilab environment which is a free analogue of the Matlab environment. To explain the principle of operation of demodulators, block diagrams and graphs of signals in time and frequency domains are shown.

Reconfigurable Logic Controller—Direct FPGA Synthesis Approach

Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel program execution is proposed. It utilize direct in hardware program implementation in field programmable devices. The paper brings a formal method of representing control programs using flow graphs and enabling single cycle computations. The developed method accepts ladder diagrams (LD) and sequential function charts (SFC), according to IEC61131-3 standard requirements. It is capable of handling logic and arithmetic computations, enabling its hardware mapping. The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies. The BDD representation of logic dependencies enables direct mapping to lookup tables of a selected FPGA family. All the above steps deliver high-performance and direct hardware implementation of the control program given by standard languages. The controller response time is short, predictable, and independent from logic conditions during program execution.

A Configurable RO-PUF for Securing Embedded Systems Implemented on Programmable Devices

Improving the security of electronic devices that support innovative critical services (digital administrative services, e-health, e-shopping, and on-line banking) is essential to lay the foundations of a secure digital society. Security schemes based on Physical Unclonable Functions (PUFs) take advantage of intrinsic characteristics of the hardware for the online generation of unique digital identifiers and cryptographic keys that allow to ensure the protection of the devices against counterfeiting and to preserve data privacy. This paper tackles the design of a configurable Ring Oscillator (RO) PUF that encompasses several strategies to provide an efficient solution in terms of area, timing response, and performance. RO-PUF implementation on programmable logic devices is conceived to minimize the use of available resources, while operating speed can be optimized by properly selecting the size of the elements used to obtain the PUF response. The work also describes the interface added to the PUF to facilitate its incorporation as hardware Intellectual Property (IP)-modules into embedded systems. The performance of the RO-PUF is proven with an extensive battery of tests, which are executed to analyze the influence of different test strategies on the PUF quality indexes. The configurability of the proposed RO-PUF allows establishing the most suitable “cost/performance/security-level” trade-off for a certain application.

On the issue of improving methods for diagnosing energy-saturated tractors with the use of microprocessor-based programmable devices of the AVR series

The article presents the rationale for the possible use of microprocessor-based programmable devices of the AVR series in order to develop the nomenclature of meters-indicators for improving the diagnostic methods, including resource-based, of energy-saturated tractors.

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach

Architecture synthesis methodology of run-time reconfigurable multi-task and multi-mode systems with self-assembling micro-architecture

Despite the success that programmable devices have enjoyed in the last two decades, architecture synthesis methodologies for Run-Time Reconfigurable (RTR) systems are still in their infancy. As the majority of consumer devices integrate multiple-functionality, the cost-effectiveness becomes the main focus of computing systems design. This thesis presents a novel architecture synthesis methodology for the cost-effective implementation of a multi-task and multi-mode workload. The proposed methodology creates a RTR system that changes its functionality in response to a dynamic environment and enables on-chip assembly of pre-constructed components by synthesizing a workload-specific static architecture. The proposed methodology presents novelties in design abstraction, partitioning method and in the procedure of deciding reconfiguration granularity. The experimental results show the cost benefits of the proposed architecture synthesis methodology saving 73% of area and 29.8% of power compared to fixed design approach