polishing pad
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2021 ◽  
Vol 11 (10) ◽  
pp. 4358
Author(s):  
Hanchul Cho ◽  
Taekyung Lee ◽  
Doyeon Kim ◽  
Hyoungjae Kim

The uniformity of the wafer in a chemical mechanical polishing (CMP) process is vital to the ultra-fine and high integration of semiconductor structures. In particular, the uniformity of the polishing pad corresponding to the tool directly affects the polishing uniformity and wafer shape. In this study, the profile shape of a CMP pad was predicted through a kinematic simulation based on the trajectory density of the diamond abrasives of the diamond conditioner disc. The kinematic prediction was found to be in good agreement with the experimentally measured pad profile shape. Based on this, the shape error of the pad could be maintained within 10 μm even after performing the pad conditioning process for more than 2 h, through the overhang of the conditioner.


2021 ◽  
Vol 10 (1) ◽  
pp. 014008
Author(s):  
N. B. Kenchappa ◽  
Ramtej Popuri ◽  
Ashwin Chockkalingam ◽  
Puneet Jawali ◽  
Shiyan Jayanath ◽  
...  

2020 ◽  
Vol 11 (1) ◽  
pp. 179
Author(s):  
Chao-Chang A. Chen ◽  
Jen-Chieh Li ◽  
Wei-Cheng Liao ◽  
Yong-Jie Ciou ◽  
Chun-Chen Chen

This study aims to develop a dynamic pad monitoring system (DPMS) for measuring the surface topography of polishing pad. Chemical mechanical planarization/polishing (CMP) is a vital process in semiconductor manufacturing. The process is applied to assure the substrate wafer or thin film on wafer that has reached the required planarization after deposition for lithographic processing of the desired structures of devices. Surface properties of polishing pad have a huge influence on the material removal rate (MRR) and quality of wafer surface by CMP process. A DPMS has been developed to analyze the performance level of polishing pad for CMP. A chromatic confocal sensor is attached on a designed fixture arm to acquire pad topography data. By swing-arm motion with continuous data acquisition, the surface topography information of pad can be gathered dynamically. Measuring data are analyzed with a designed FFT filter to remove mechanical vibration and disturbance. Then the pad surface profile and groove depth can be calculated, which the pad’s index PU (pad uniformity) and PELI (pad effective lifetime index) are developed to evaluate the pad’s performance level. Finally, 50 rounds of CMP experiments have been executed to investigate the correlations of MRR and surface roughness of as-CMP wafer with pad performance. Results of this study can be used to monitor the pad dressing process and CMP parameter evaluation for production of IC devices.


2020 ◽  
Vol 66 ◽  
pp. 577-592
Author(s):  
Urara Satake ◽  
Senju Matsui ◽  
Toshiyuki Enomoto
Keyword(s):  

2020 ◽  
Vol 9 (1) ◽  
pp. 182-189 ◽  
Author(s):  
Gaoyang Zhao ◽  
Zhen Wei ◽  
Weilei Wang ◽  
Daohuan Feng ◽  
Aoxue Xu ◽  
...  

AbstractWith the development of integrated circuit technology, especially after entering the sub-micron process, the reduction of critical dimensions and the realization of high-density devices, the flatness between integrated circuit material layers is becoming more and more critical. Because conventional mechanical polishing methods inevitably produce scratches of the same size as the device in metal or even dielectric layers, resulting in depth of field and focus problems in lithography. The first planarization technique to achieve application is spin on glass (SOG) technology. However, this technology will not only introduce new material layers, but will also fail to achieve the global flattening required by VLSI and ULSI technologies. Moreover, the process instability and uniformity during spin coating do not meet the high flatness requirements of the wafer surface. Also, while some techniques such as reverse etching and glass reflow can achieve submicron level regional planarization. After the critical dimension reaches 0.35 microns (sub-micron process), the above methods cannot meet the requirements of lithography and interconnect fabrication. In the 1980s, IBM first introduced the chemical mechanical polishing (CMP) technology used to manufacture precision optical instruments into its DRAM manufacturing [1]. With the development of technology nodes and critical dimensions, CMP technology has been widely used in the Front End Of Line (FEOL) and Back End Of Line (BEOL) processes [2]. Since the invention of chemical mechanical polishing, scientists have not stopped studying its internal mechanism. From the earliest Preston Formula (1927) to today’s wafer scale, chip scale, polishing pad contact, polishing pad - abrasive - wafer contact and material removal models, there are five different scale models from macro to the micro [3]. Many research methods, such as contact mechanics, multiphase flow kinetics, chemical reaction kinetics, molecular dynamics, etc., have been applied to explain the principles of chemical mechanical polishing to establish models. This paper mainly introduces and summarizes the different models of chemical mechanical polishing technology. The various application scenarios and advantages and dis-advantages of the model are discussed, and the development of modeling technology is introduced.


2020 ◽  
Vol 47 (4) ◽  
pp. 0403001
Author(s):  
孙荣康 Sun Rongkang ◽  
王金栋 Wang Jindong ◽  
成聪 Cheng Cong ◽  
廖德锋 Liao Defeng

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