scholarly journals A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

2021 ◽  
Vol 11 (3) ◽  
pp. 32
Author(s):  
Hasan Irmak ◽  
Federico Corradi ◽  
Paul Detterer ◽  
Nikolaos Alachiotis ◽  
Daniel Ziener
Keyword(s):  
Neural Network ◽  
Reconfigurable Architecture ◽  
Frame Rate ◽  
Model Parameters ◽  
Hybrid Architecture ◽  
Throughput Performance ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Field Programmable ◽  
Reconfigurable Processing

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.

Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems

2014 ◽  
pp. 347-371 ◽  
Author(s):  
Naim Harb ◽  
Smail Niar ◽  
Mazen A. R. Saghir
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Transportation Systems ◽  
Base System ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Mtt Algorithm

Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.

Methodology for Implementing Scalable Run-Time Reconfigurable Devices

2011 ◽  
Vol 57 (2) ◽  
pp. 177-183 ◽  
Author(s):  
Łukasz Kotynia ◽  
Piotr Amrozik ◽  
Andrzej Napieralski
Keyword(s):  
Dynamically Reconfigurable ◽  
Fine Grained ◽  
Operating Modes ◽  
Reconfigurable Devices ◽  
Multiple Data ◽  
Implementation Techniques ◽  
Field Programmable ◽  
Reconfigurable Processing ◽  
Run Time ◽  
Implementation Methodology

Methodology for Implementing Scalable Run-Time Reconfigurable Devices The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.

Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio

2020 ◽  
pp. 2150042
Author(s):  
Islam Ahmed ◽  
Ahmed Nader Mohieldin ◽  
Hassan Mostafa
Keyword(s):  
Software Defined Radio ◽  
Computer Aided Design ◽  
Functional Verification ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Design Cycle ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Aided Design

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle.

HyDRA: Hybrid Dynamically Reconfigurable Architecture for DSP Applications

2016 ◽  
Vol E99.C (7) ◽  
pp. 866-877 ◽  
Author(s):  
Abdulfattah M. OBEID ◽  
Syed Manzoor QASIM ◽  
Mohammed S. BENSALEH ◽  
Abdullah A. ALJUFFRI
Keyword(s):  
Reconfigurable Architecture ◽  
Dynamically Reconfigurable ◽  
Dsp Applications ◽  
Dynamically Reconfigurable Architecture

scholarly journals A Method of Fast Segmentation for Banana Stalk Exploited Lightweight Multi-Feature Fusion Deep Neural Network

Machines ◽  
2021 ◽  
Vol 9 (3) ◽  
pp. 66
Author(s):  
Tianci Chen ◽  
Rihong Zhang ◽  
Lixue Zhu ◽  
Shiang Zhang ◽  
Xiaomin Li
Keyword(s):  
Neural Network ◽  
Execution Time ◽  
Deep Neural Network ◽  
Feature Fusion ◽  
Frame Rate ◽  
Light Conditions ◽  
Segmentation Method ◽  
Segmentation Accuracy ◽  
Automatic Picking ◽  
Changing Light

In an orchard environment with a complex background and changing light conditions, the banana stalk, fruit, branches, and leaves are very similar in color. The fast and accurate detection and segmentation of a banana stalk are crucial to realize the automatic picking using a banana picking robot. In this paper, a banana stalk segmentation method based on a lightweight multi-feature fusion deep neural network (MFN) is proposed. The proposed network is mainly composed of encoding and decoding networks, in which the sandglass bottleneck design is adopted to alleviate the information a loss in high dimension. In the decoding network, a different sized dilated convolution kernel is used for convolution operation to make the extracted banana stalk features denser. The proposed network is verified by experiments. In the experiments, the detection precision, segmentation accuracy, number of parameters, operation efficiency, and average execution time are used as evaluation metrics, and the proposed network is compared with Resnet_Segnet, Mobilenet_Segnet, and a few other networks. The experimental results show that compared to other networks, the number of network parameters of the proposed network is significantly reduced, the running frame rate is improved, and the average execution time is shortened.

scholarly journals Enhanced Neural Network Model for Worldwide Estimation of Weighted Mean Temperature

2021 ◽  
Vol 13 (12) ◽  
pp. 2405
Author(s):  
Fengyang Long ◽  
Chengfa Gao ◽  
Yuxiang Yan ◽  
Jinling Wang
Keyword(s):  
Neural Network ◽  
Real Time ◽  
Model Performance ◽  
Global Scale ◽  
Radiosonde Data ◽  
Model Parameters ◽  
Measured Temperature ◽  
Weighted Mean ◽  
Weighted Mean Temperature ◽  
Application Scope

Precise modeling of weighted mean temperature (Tm) is critical for realizing real-time conversion from zenith wet delay (ZWD) to precipitation water vapor (PWV) in Global Navigation Satellite System (GNSS) meteorology applications. The empirical Tm models developed by neural network techniques have been proved to have better performances on the global scale; they also have fewer model parameters and are thus easy to operate. This paper aims to further deepen the research of Tm modeling with the neural network, and expand the application scope of Tm models and provide global users with more solutions for the real-time acquisition of Tm. An enhanced neural network Tm model (ENNTm) has been developed with the radiosonde data distributed globally. Compared with other empirical models, the ENNTm has some advanced features in both model design and model performance, Firstly, the data for modeling cover the whole troposphere rather than just near the Earth’s surface; secondly, the ensemble learning was employed to weaken the impact of sample disturbance on model performance and elaborate data preprocessing, including up-sampling and down-sampling, which was adopted to achieve better model performance on the global scale; furthermore, the ENNTm was designed to meet the requirements of three different application conditions by providing three sets of model parameters, i.e., Tm estimating without measured meteorological elements, Tm estimating with only measured temperature and Tm estimating with both measured temperature and water vapor pressure. The validation work is carried out by using the radiosonde data of global distribution, and results show that the ENNTm has better performance compared with other competing models from different perspectives under the same application conditions, the proposed model expanded the application scope of Tm estimation and provided the global users with more choices in the applications of real-time GNSS-PWV retrival.

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