scholarly journals A 5–50 GHz SiGe BiCMOS Linear Transimpedance Amplifier with 68 dBΩ Differential Gain towards Highly Integrated Quasi-Coherent Receivers

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2349
Author(s):  
Guillermo Silva Valdecasa ◽  
Jose A. Altabas ◽  
Monika Kupska ◽  
Jesper Bevensee Jensen ◽  
Tom K. Johansen
Keyword(s):  
System Integration ◽  
High Speed ◽  
Direct Detection ◽  
Scale Up ◽  
Gain Control ◽  
Point System ◽  
Cell Stage ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Coherent Receivers

Quasi-coherent optical receivers have recently emerged targeting access networks, offering improved sensitivity and reach over direct-detection schemes at the expense of a higher receiver bandwidth. Higher levels of system integration together with sufficiently wideband front-end blocks, and in particular high-speed linear transimpedance amplifiers (TIAs), are currently demanded to reduce cost and scale up receiver data rates. In this article, we report on the design and testing of a linear TIA enabling high-speed quasi-coherent receivers. A shunt-feedback loaded common-base topology is adopted, with gain control provided by a subsequent Gilbert cell stage. The circuit was fabricated in a commercial 130 nm SiGe BiCMOS technology and has a bandpass characteristic with a 3 dB bandwidth in the range of 5–50 GHz. A differential transimpedance gain of 68 dBΩ was measured, with 896 mVpp of maximum differential output swing at the 1 dB compression point. System experiments in a quasi-coherent receiver demonstrate an optical receiver sensitivity of −30.5 dBm (BER = 1 × 10−3) at 10 Gbps, and −26 dBm (BER = 1 × 10−3) at 25 Gbps. The proposed TIA represents an enabling component towards highly integrated quasi-coherent receivers.

scholarly journals 10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 563
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Communication Systems ◽  
Power Efficiency ◽  
High Speed ◽  
Closed Loop ◽  
Dynamic Range ◽  
Data Converters ◽  
Fully Differential ◽  
Biquad Filter ◽  
Bicmos Technology ◽  
Sige Bicmos

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wireless Transceivers ◽  
Digital To Analog Converter ◽  
Bicmos Technology ◽  
Analog Converter ◽  
Sige Bicmos ◽  
Digital To Analog ◽  
On Chip ◽  
Binary Weighted

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

Analysis and Design of a Linear Digital Programmable Gain Amplifier in a 0.13 µm SiGe BiCMOS technology

Frequenz ◽  
2017 ◽  
Vol 71 (3-4) ◽  
Author(s):  
Xuan-Quang Du ◽  
Anselm Knobloch ◽  
Markus Grözing ◽  
Matthias Buck ◽  
Manfred Berroth
Keyword(s):  
Harmonic Distortion ◽  
Gain Control ◽  
Step Size ◽  
Analysis And Design ◽  
Fully Differential ◽  
Gain Error ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Programmable Gain Amplifier ◽  
Programmable Gain

AbstractThis paper presents the analysis and the design of a fully-differential digital programmable gain amplifier (PGA) in a 0.13 µm BiCMOS technology. The PGA has a gain control range of 31 dB with 1 dB gain step size and consumes 284 mW from a 3.6 V power supply. At a maximum gain of 25 dB, the PGA exhibits a 3-dB bandwidth of 10.1 GHz. The measured gain error for all 32 possible gain settings is between –0.19/+0.46 dB at 1 GHz. Up to 13 GHz the third harmonic distortion

An E-band Variable Gain Amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Dynamic Range ◽  
Gain Control ◽  
Variable Gain Amplifier ◽  
Control Range ◽  
Variable Gain ◽  
Bicmos Technology ◽  
Commercial Technology ◽  
Sige Bicmos ◽  
Analysis Design

Abstract Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control range and linearity. A 1 dB bandwidth ranging from 80 to 100 GHz, a 24 dB gain control range and a −11.5 dBm input 1 dB compression point have been measured.

DESIGN CONSIDERATIONS FOR INTEGRATED MODULATOR DRIVERS IN SILICON GERMANIUM TECHNOLOGY

2005 ◽  
Vol 15 (03) ◽  
pp. 477-495 ◽  
Author(s):  
SHANTHI PAVAN ◽  
MAURICE TARSIA ◽  
STEFFEN KUDSZUS ◽  
DAVID PRITZKAU
Keyword(s):  
Power Supply ◽  
Silicon Germanium ◽  
High Speed ◽  
Design Considerations ◽  
Trade Offs ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Present Design ◽  
Simulation Results ◽  
Modulator Driver

We present design considerations for high speed high swing differential modulator drivers in SiGe BiCMOS technology. Trade-offs between lumped and distributed designs, and linear and limiting amplifiers are examined. The design of a 6 V output modulator driver is discussed in detail. The driver features a unique bias generation and distribution circuit that enables low power-supply operation. Simulation results and measurements are given.

A 10 GB/S EQUALIZER WITH INTEGRATED CLOCK AND DATA RECOVERY FOR OPTICAL COMMUNICATION SYSTEMS

2005 ◽  
Vol 15 (03) ◽  
pp. 525-548 ◽  
Author(s):  
D. S. MCPHERSON ◽  
H. TRAN ◽  
P. POPESCU
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Automatic Gain Control ◽  
Polarization Mode Dispersion ◽  
Gain Control ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Decision Feedback ◽  
Bicmos Technology ◽  
Feedforward Equalizer

A 10 Gb/s analog continuous-time equalizer with integrated clock and data recovery circuit is presented. It is designed to recover signals degraded by chromatic and polarization mode dispersion. The key components in the design are a feedforward equalizer and a decision feedback equalizer, the parameters of which are electronically adjustable. Both circuit blocks are fully described and characterized with emphasis on minimizing self-induced distortion and maximizing high-speed performance. In addition to the equalizer and the clock and data recovery, the circuit also includes an integrated automatic gain control. The circuit is implemented in a commercial 0.18 μm SiGe BiCMOS technology and consumes 900 mW. The capacity of the equalizer to mitigate signal impairments is demonstrated using three electrically generated channels.

SiGe HBT/BiCMOS Technologies and their Applications to Communication ICs/LSIs

2004 ◽  
Vol 809 ◽  
Author(s):  
Katsuya Oda ◽  
Katsuyoshi Washio ◽  
Takashi Hashimoto
Keyword(s):  
High Speed ◽  
Cutoff Frequency ◽  
Clock Rate ◽  
Sige Hbt ◽  
Selective Epitaxial Growth ◽  
Communications Systems ◽  
Ultra High Speed ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Doping Profiles

ABSTRACTSelf-aligned ultra-high-speed SiGe HBTs were developed by using selective epitaxial growth (SEG) technology. The use of HCl-free SEG, incorporation of C, and optimization of doping profiles significantly improves the performance of the HBT, producing a transistor with a high cutoff frequency of 170 GHz and a maximum oscillation frequency of 204 GHz, for a minimum ECL gate delay time of 4.8 ps. This is applied in a 16:1 MUX with a maximum clock rate of 57 GHz. A 0.13-μm SiGe BiCMOS technology is also realized without any degradation of CMOS due to the high stability of SiGe HBTs. Furthermore, the structure of SiGe HBT is optimized for an emitter scaled down towards 100 nm, mainly through the use of a funnel-shaped emitter electrode to reduce both emitter and base resistances. High-speed operation of a static frequency divider demonstrates the advantage of SiGe HBTs for ultra-high-speed communications systems.

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