scholarly journals Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 991
Author(s):  
Joseph Riad ◽  
Sergio Soto-Aguilar ◽  
Johan J. Estrada-López ◽  
Oscar Moreira-Tamayo ◽  
Edgar Sánchez-Sinencio
Keyword(s):  
Cmos Technology ◽  
Common Mode ◽  
Operational Transconductance Amplifiers ◽  
Fully Differential ◽  
Trade Offs ◽  
Active Rc Filter ◽  
Transconductance Amplifiers ◽  
Two Stages ◽  
The Impact

Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the multi-loop implementation with respect to the single-loop case.

Fully Differential Class-AB OTA with Improved CMRR

2017 ◽  
Vol 26 (11) ◽  
pp. 1750169 ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Gaetano Parisi ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Cmos Technology ◽  
Current Mirror ◽  
Differential Mode ◽  
Common Mode ◽  
Common Mode Rejection Ratio ◽  
Class Ab ◽  
Fully Differential ◽  
Rejection Ratio ◽  
Mode Behavior ◽  
The Common

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90[Formula: see text]dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated.

Preliminary Design and Performance of Counter Rotating Turbines for Open Rotors: Part II — 0-D Methodology and Case Study for a 160 PAX Aircraft

2016 ◽  
Author(s):  
Pablo Bellocq ◽  
Inaki Garmendia ◽  
Jordane Legrand ◽  
Vishal Sethi
Keyword(s):  
Design Methodology ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Preliminary Design ◽  
Regulatory Constraints ◽  
Trade Offs ◽  
And Performance ◽  
The Impact

Direct Drive Open Rotors (DDORs) have the potential to significantly reduce fuel consumption and emissions relative to conventional turbofans. However, this engine architecture presents many design and operational challenges both at engine and aircraft level. At preliminary design stages, a broad design space exploration is required to identify potential optimum design regions and to understand the main trade offs of this novel engine architecture. These assessments may also aid the development process when compromises need to be performed as a consequence of design, operational or regulatory constraints. Design space exploration assessments are done with 0-D or 1-D models for computational purposes. These simplified 0-D and 1-D models have to capture the impact of the independent variation of the main design and control variables of the engine. Historically, it appears that for preliminary design studies of DDORs, Counter Rotating Turbines (CRTs) have been modelled as conventional turbines and therefore it was not possible to assess the impact of the variation of the number of stages (Nb) of the CRT and rotational speed of the propellers. Additionally, no preliminary design methodology for CRTs was found in the public domain. Part I of this two-part publication proposes a 1-D preliminary design methodology for DDOR CRTs which allows an independent definition of both parts of the CRT. A method for calculating the off-design performance of a known CRT design is also described. In Part II, a 0-D design point efficiency calculation for CRTs is proposed and verified with the 1-D methods. The 1-D and 0-D CRT models were used in an engine control and design space exploration case study of a DDOR with a 4.26m diameter an 10% clipped propeller for a 160 PAX aircraft. For this application: • the design and performance of a 20 stage CRT rotating at 860 rpm (both drums) obtained with the 1-D methods is presented. • differently from geared open rotors, negligible cruise fuel savings can be achieved by an advanced propeller control. • for rotational speeds between 750 and 880 rpm (relatively low speeds for reduced noise), 22 and 20 stages CRTs are required. • engine weight can be kept constant for different design rotational speeds by using the minimum required Nb. • for any target engine weight, TOC and cruise SFC are reduced by reducing the rotational speeds and increasing Nb (also favourable for reducing CRP noise). However additional CRT stages increase engine drag, mechanical complexity and cost.

scholarly journals Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1410
Author(s):  
Luis Henrique Rodovalho ◽  
Orazio Aiello ◽  
Cesar Ramos Rodrigues
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Gain ◽  
Design Environment ◽  
Operational Transconductance Amplifiers ◽  
Gain Enhancement ◽  
Transconductance Amplifiers ◽  
Forward Body Bias ◽  
The Cost ◽  
The Impact

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

scholarly journals Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 983 ◽  
Author(s):  
Pedro Toledo ◽  
Paolo Crovetti ◽  
Hamilton Klimach ◽  
Sergio Bampi
Keyword(s):  
Pulse Width Modulation ◽  
Low Voltage ◽  
Process Variations ◽  
Pulse Modulation ◽  
Silicon Area ◽  
Operational Transconductance Amplifiers ◽  
Static Calibration ◽  
Digital Pulse ◽  
Transconductance Amplifiers ◽  
The Impact

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

scholarly journals Temporal changes in greenspace in a highly urbanized region

2011 ◽  
Vol 7 (5) ◽  
pp. 763-766 ◽  
Author(s):  
Martin Dallimer ◽  
Zhiyao Tang ◽  
Peter R. Bibby ◽  
Paul Brindley ◽  
Kevin J. Gaston ◽  
...  
Keyword(s):  
Land Use ◽  
Urban Areas ◽  
National Level ◽  
Urban Land Use ◽  
Policy Reforms ◽  
Trade Offs ◽  
Dramatic Shift ◽  
Urbanized Region ◽  
The Impact

The majority of the world's population now lives in towns and cities, and urban areas are expanding faster than any other land-use type. In response to this phenomenon, two opposing arguments have emerged: whether cities should ‘sprawl’ into the wider countryside, or ‘densify’ through the development of existing urban greenspace. However, these greenspaces are increasingly recognized as being central to the amelioration of urban living conditions, supporting biodiversity conservation and ecosystem service provision. Taking the highly urbanized region of England as a case study, we use data from a variety of sources to investigate the impact of national-level planning policy on temporal patterns in the extent of greenspace in cities. Between 1991 and 2006, greenspace showed a net increase in all but one of 13 cities. However, the majority of this gain occurred prior to 2001, and greenspace has subsequently declined in nine cities. Such a dramatic shift in land use coincides with policy reforms in 2000, which favoured densification. Here, we illustrate the dynamic and policy-responsive nature of urban land use, thereby highlighting the need for a detailed investigation of the trade-offs associated with different mechanisms of urban densification to optimize and secure the diverse benefits associated with greenspaces.

Testing fully differential amplifiers using common mode feedback circuit: A case study

2015 ◽  
Author(s):  
Isis D. Bender ◽  
Guilherme S. Cardoso ◽  
Arthur C. de Oliveira ◽  
Lucas C. Severo ◽  
Alessandro Girardi ◽  
...  
Keyword(s):  
Feedback Circuit ◽  
Common Mode ◽  
Differential Amplifiers ◽  
Fully Differential

scholarly journals CMOS OTA-Based Filters for Designing Fractional-Order Chaotic Oscillators

2021 ◽  
Vol 5 (3) ◽  
pp. 122
Author(s):  
Martín Alejandro Valencia-Ponce ◽  
Perla Rubí Castañeda-Aviña ◽  
Esteban Tlelo-Cuautle ◽  
Victor Hugo Carbajal-Gómez ◽  
Victor Rodolfo González-Díaz ◽  
...  
Keyword(s):  
Fractional Order ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Chaotic Oscillators ◽  
Operational Transconductance Amplifiers ◽  
Fractional Order Integrator ◽  
The Mathematical Model ◽  
Good Agreement

Fractional-order chaotic oscillators (FOCOs) have shown more complexity than integer-order chaotic ones. However, the majority of electronic implementations were performed using embedded systems; compared to analog implementations, they require huge hardware resources to approximate the solution of the fractional-order derivatives. In this manner, we propose the design of FOCOs using fractional-order integrators based on operational transconductance amplifiers (OTAs). The case study shows the implementation of FOCOs by cascading first-order OTA-based filters designed with complementary metal-oxide-semiconductor (CMOS) technology. The OTAs have programmable transconductance, and the robustness of the fractional-order integrator is verified by performing process, voltage and temperature variations as well as Monte Carlo analyses for a CMOS technology of 180 nm from the United Microelectronics Corporation. Finally, it is highlighted that post-layout simulations are in good agreement with the simulations of the mathematical model of the FOCO.

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