MODEL OF INFORMATION INTERACTION BETWEEN ELEMENTS OF MULTILEVEL SYSTEM OF DIGITAL TWINS

One of the solutions to the problem of spatio-temporal data anisotropy is the use of a multilevel system of digital twins based on the corresponding industry models and the updated archive data base. The application of this approach has successfully proved itself in information systems for monitoring the parameters of the geomagnetic field and its variations, providing spatio-temporal interpolation of geomagnetic data with an accuracy of 0.81 nT in magnetically quiet periods. At the same time, the problem of information interaction between the levels of the system of digital twins remained unresolved, which is greatly aggravated by the constantly growing volume of data and their heterogeneous nature. The paper proposes a solution to the indicated problem by means of a formalized mechanism for packaging space-time information, in which the identification of data sources is performed on the basis of a hierarchical binary tokenization system. In addition, the proposed software implementation of such an approach is considered, a distinctive feature of which is the combination of traditional clientserver and innovative serverless architectures to implement a highly loaded reactive web application for working with analyzed data. The main stages of the implementation of information interaction are highlighted and programmatically formalized - from obtaining initial information from its sources to verifying data, analyzing them, processing and forming the output information flow of the system. The results of the computational experiments carried out on the example of the problem of monitoring the parameters of the Earth's magnetic field and its variations confirmed the effectiveness of the proposed solutions, expressed both in increasing the reactivity of web-based applications and in increasing the computational speed of formation and filling of information storages that aggregate information from distributed heterogeneous sources.

An Alternative Concept for Maintaining Occupant Compartment Integrity During Narrow Overlap Vehicle Crashes

Front Small Overlap (FSO), a new test mode introduced by IIHS is used for differentiating North American market vehicles on their safety ratings with the Top Safety Pick (TSP) status. Current paper describes a production ready version of a non-traditional (door insert) concept. Small overlap test mode demands occupant cage integrity which can be achieved from structural countermeasures in the Side Sill, A-pillar or Front body hinge pillar. These structural measures add mass and need lead time for development (not feasible for existing vehicles). Current study describes door insert design that can be incorporated into the doors for providing improved strength for small overlap loading conditions. Paper investigates composites / structural plastic design onto existing impact door beams (Within the available packaging space). The door insert, along with improved CAB deployment capability, would provide improvement on existing vehicle safety ratings.

A New Package Structure for High Speed eStorages

Mobile storage density per chip (NAND, DRAM, etc) has increased as well with ever growing usage of high speed mobile systems. For these requirements, various eStoarge solutions (eMMC, eMCP, etc) have been developed. To optimize high speed and high density requirements in a tighter limited packaging space, we propose a new package structure using RDL(Re-Distribution Layer) on chips for optimal design with a high interface speed, smaller and cheaper package in this paper.

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

3D & System-in-Package Development with the Redistributed Chip Package (RCP)

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology. Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.

An Efficient Method for Detecting Packaging Supporting Space

This paper presents an efficient method to generate packaging space that can be used to create molded foam. This method first reduces the number of facets presenting the product and then detects heights of supporting lines from an evenly spaced mesh grid on the bottom space of a pre-defined bounding box. The height of each supporting line is further relaxed and smoothed to form the final supporting surface. Based on the supporting surface, an STL format is created so it can be fabricated using RP machines. Three examples are presented to demonstrate this method.