3D & System-in-Package Development with the Redistributed Chip Package (RCP)

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002374-002398
Author(s):  
Zhiwei (Tony) Gong ◽  
Scott Hayes ◽  
Navjot Chhabra ◽  
Trung Duong ◽  
Doug Mitchell ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Systems On Chip ◽  
3D Packaging ◽  
Packaging Space ◽  
Advanced Packaging ◽  
On Chip ◽  
Imaging Sensors ◽  
3D Applications

Fan-out wafer level packaging (FO-WLP) has become prevalent in past two years as a package option with large number of pin count. As the result of early development, the single die packages with single-sided redistribution has reached the maturity to take off. While the early applications start to pay back the investment on the technology, the developments have shifted to more advanced packaging solutions with System-in-Package (SiP) and 3D applications. The nature of the FO-WLP interconnect along with the material compatibility and process capability of the Redistributed Chip Package (RCP) have enabled Freescale to create novel System-in-Package (SiP) solutions not possible in more traditional packaging technologies or Systems-on-Chip. Simple SiPs using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or a substrate based multi-chip module (MCM). More complex three dimensional (3D) SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMDs, CMOS, GaAs, MEMS, imaging sensors or IPDs gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. The following paper further discusses SiP advantages, applications and examples created with the RCP technology. Rozalia/Ron ok move from 2.5/3D to Passive 1-4-12.

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001486-001519
Author(s):  
Curtis Zwenger ◽  
JinYoung Khim ◽  
YoonJoo Khim ◽  
SeWoong Cha ◽  
SeungJae Lee ◽  
...  
Keyword(s):  
Low Cost ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Structures ◽  
Wafer Level Packaging ◽  
Functional Convergence ◽  
3D Packaging ◽  
Improved Design ◽  
On Chip ◽  
Mobile Handset

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

2013 ◽  
Vol 2013 (1) ◽  
pp. 000447-000451 ◽  
Author(s):  
Michael Vincent ◽  
Doug Mitchell ◽  
Jason Wright ◽  
Yap Weng Foong ◽  
Alan Magnus ◽  
...  
Keyword(s):  
System Integration ◽  
System Performance ◽  
Electrical Characterization ◽  
Emerging Technology ◽  
Volumetric Efficiency ◽  
Wafer Level ◽  
Novel Technologies ◽  
3D Packaging ◽  
Packaging Space ◽  
On Chip

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

Reliability and Performance Improvements of 3D System-in-Packages in Fan-Out Wafer Level Packaging

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001458-001485
Author(s):  
Scott Hayes ◽  
Tony Gong ◽  
Doug Mitchell ◽  
Michael Vincent ◽  
Jason Wright ◽  
...  
Keyword(s):  
Wafer Level ◽  
Low Loss ◽  
3D Integration ◽  
Performance Improvements ◽  
Wafer Level Packaging ◽  
Effective System ◽  
3D Packaging ◽  
And Performance ◽  
Imaging Sensors ◽  
2D And 3D

Recent development efforts for fan-out wafer level packaging (FO-WLP) have focused on system-in-package (SiP) solutions using both 2D and 3D packaging structures. Creating connections between the various elements of the system is one of the critical requirements of the packaging technology. The connections must provide a low loss pathway, exhibit manufacturability and prove reliable. Effective system connections enable complex yet volumetrically and electrically efficient systems to be constructed. The combination of various system elements including, but not limited to, SMDs, CMOS, GaAs, MEMS, power devices, imaging sensors or IPDs gives system designers the capability to generate novel systems and differentiating solutions. Both 2D and 3D SiPs based upon the Redistributed Chi Package (RCP) have been developed for consumer, defense and medical applications. In RCP (i.e. FO-WLP), 2D systems are readily achieved through the use of existing packaging processes, materials and structures. For 3D embodiments, the FO-WLP technology must be expanded. 3D integration in FO-WLP can be achieved with the use of package-on-package (PoP), embedded substrates, package edge connections, die stacking or even TSV approaches. However, a more typical solution to the 3D integration challenge is the through package via (TPV). TPVs can resemble substrate vias but their construction is typically different. Regardless of materials selected or processes used to create the TPV, system connections using a TPV will require a certain level of performance and reliability. Reliability and performance improvements to the 3D RCP technology will be presented.

Improved compensation for a reduction stepper to meet the challenges for advanced packaging applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000814-000819 ◽  
Author(s):  
James E Webb ◽  
Steven Gardner ◽  
Elvino DaSilveira
Keyword(s):  
Leading Edge ◽  
Image Features ◽  
Wafer Level ◽  
Projection Lens ◽  
Wafer Level Packaging ◽  
Alignment System ◽  
Wide Range ◽  
Advanced Packaging ◽  
Volume Production ◽  
Mix And Match

Advanced packaging manufacturers require steppers that will provide solutions for the challenges encountered with new advances in wafer-level packaging technologies such as TSV, eWLB, silicon and glass interposers being utilized in leading edge mobile devices. Step and repeat photolithography systems capable of finer imaging with tighter overlay are being introduced to meet the challenging manufacturing requirements associated with the mix and match needed for volume production on larger wafers. A 2X reduction stepper with unique features incorporated that extend the range of compensation is necessary to achieve the tighter specifications needed for many advanced packaging applications printed on 300 to 450mm wafers. A high throughput projection optical system is used to expose circuit patterns from a reticle mask onto a substrate to image features with the optimal fidelity required for advanced packaging technologies. The camera incorporates 350–450nm light from a mercury arc lamp that is transmitted through the mask containing circuit patterns. The imaging field prints a large 52mm × 66mm area in a single exposure. These features enable a system to process wafers in fewer shots which result in higher throughput using lower power. Substrates are positioned with a precise X, Y, Θ stage by locating marks using an off-axis, bright field alignment system with fully trainable mark feature capability. The approach results in precisely placed features within a layer and from layer to layer without directly referencing the reticle. The integrated metrology and precision positioning subsystem technologies are combined with a low distortion projection lens and a wide range of adjustments, allowing the stepper to be integrated into a production line in a mix and match setup with other lithography systems. This equipment can be used to image critical layers on substrates while ensuring grid registration and alignment with other lithography systems that are also printing images in the same process line. Several important global and intra-field image placement relationships for devices requiring multiple layer patterning have been combined in the stepper matching correction software. Further adjustment to the tool can be made to improve overlay when incorporated with fab-wide yield management software for automated, real-time process control. The types of adjustments needed and techniques that can be applied to compensate for image placement errors over large areas are discussed.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

scholarly journals System-on-chip testing

2019 ◽  
Author(s):  
Παναγιώτης Γεωργίου
Keyword(s):  
Integrated Circuits ◽  
Three Dimensional ◽  
Rectangle Packing ◽  
3D Ics ◽  
Systems On Chip ◽  
Self Test ◽  
Chip Testing ◽  
On Chip ◽  
Silicon Vias ◽  
Access Mechanisms

Διανύουμε ήδη την εποχή του "Ίντερνετ των Πραγμάτων". Οι κοινές συσκευές που χρησιμοποιούμε καθημερινά, συνδέονται μεταξύ τους και γίνονται "εξυπνότερες" με ραγδαίους ρυθμούς. Σε κάθε τέτοια συσκευή βρίσκεται ένα Σύστημα σε Ολοκληρωμένο (Systems-On-Chip ή SoC). Το SoC εξελίσσεται συνεχώς, για να ικανοποιηθούν οι συνεχώς αυξανόμενες απαιτήσεις της νέας εποχής. Τα τρι-διάστατα ολοκληρωμένα κυκλώματα (three-dimensional integrated circuits - 3D-ICs) είναι μια υποσχόμενη λύση για να ικανοποιήσουν τις απαιτήσεις τις νέας εποχής και φαίνεται να εξασφαλίζουν τη συνέχιση του Νόμου του Moore στο άμεσο μέλλον. Τα 3D-ICs πετυχαίνουν υψηλότερη πυκνότητα πυλών και καλύτερη απόδοση από τα συμβατικά SoC και μειώνουν το κόστος διασύνδεσης και κατανάλωσης. Πρόσφατα, οι κατασκευαστικές εταιρείες ολοκληρωμένων συστημάτων κυκλοφόρησαν προϊόντα βασισμένα σε 3D-ICs. Η έρευνα αυτή εστιάζει στην ανάπτυξη νέων αρχιτεκτονικών μηχανισμού πρόσβασης ελέγχου (Test Access Mechanisms - TAMs) και νέων μεθόδων χρονοπρογραμματισμού ελέγχου ορθής λειτουργίας για 3D-SoCs, οι οποίες εκμεταλλεύονται την υψηλή ταχύτητα που προσφέρουν οι ειδικές κάθετες διασυνδέσεις μέσω-πυριτίου (Through Silicon Vias - TSVs), ενώ η κατανάλωση ισχύος και η θερμότητα πρέπει να διατηρηθούν κάτω από ορισμένα επίπεδα. Εισάγουμε μία νέα αρχιτεκτονική TAM για 3D SoCs, η οποία ελαχιστοποιεί το χρόνο ελέγχου ορθής λειτουργίας, το πλήθος των TSVs και τις γραμμές της αρχιτεκτονικής TAM που χρησιμοποιούνται για να μεταφερθούν τα δεδομένα ελέγχου. Ο χρονοπρογραμματισμός του ελέγχου ορθής λειτουργίας υπολογίζεται από μία αποδοτική μέθοδο χρονικής πολυπλεξίας και μία πολύ αποδοτική μέθοδο βελτιστοποίησης που βασίζεται στους αλγορίθμους rectangle-packing και simulated-annealing. Πειραματικά αποτελέσματα δείχνουν έως και 9.6 φορές εξοικονόμηση στο χρόνο ελέγχου με την προτεινόμενη μέθοδο, ειδικά κάτω από αυστηρά όρια για την κατανάλωση ισχύος και τη θερμότητα. Η προηγούμενη μέθοδος είναι συμβατή μόνο με TAMs που βασίζονται σε αρτηρίες (buses), οι οποίες απαιτούν διασυνδέσεις μεγάλου μήκους και πολλά buffers σε κάθε επίπεδο του 3D-IC, επομένως δεν καταφέρνουν να εκμεταλλευτούν πλήρως τις υψηλές συχνότητες των TSVs. Προτείνουμε μία νέα αρχιτεκτονική TAM βασισμένη στη χρονική πολυπλεξία, που χρησιμοποιεί σειριακές αλυσίδες (daisy-chains) για να ξεπεράσουμε τους περιορισμούς της προηγούμενης μεθόδου. Η μέθοδος αυτή προσφέρει μεγαλύτερα κέρδη όσον αφορά το χρόνο ελέγχου ορθής λειτουργίας και το κόστος διασύνδεσης. Η έρευνα αυτή εστιάζει στη βελτίωση ανίχνευσης σφαλμάτων συσκευών βασιζόμενων σε επεξεργαστή. Οι ολοένα αυξανόμενες απαιτήσεις της αγοράς για υψηλότερη υπολογιστική απόδοση σε μικρότερο κόστος και χαμηλότερη κατανάλωση ισχύος, οδηγεί τους κατασκευαστές στην ανάπτυξη νέων μικροεπεξεργαστών, που εισάγουν νέες προκλήσεις στον έλεγχο συσκευών βασιζόμενων σε επεξεργαστή. Η ανάγκη ελέγχου των συσκευών αυτών κατά τη διάρκεια της κανονικής τους λειτουργίας, επιβάλλουν τη συμπληρωματική χρήση μεθόδων ελέγχου που δεν επηρεάζουν τη λειτουργία, όπως ο «αυτοέλεγχος βασισμένος σε λογισμικό» (Software-Based Self-Test - SBST). Οι περισσότερες τεχνικές SBST στοχεύουν μόνο το μοντέλο σφαλμάτων stuck-at, που δεν αρκεί για την ανίχνευση πολλών σφαλμάτων. Επίσης, οι τεχνικές SBST απαιτούν εκτενή ανθρώπινη ενασχόληση με μεγάλους χρόνους ανάπτυξης των προγραμμάτων ελέγχου. Επιπλέον, περιλαμβάνουν την κοστοβόρα, από άποψη υπολογιστική ισχύος, εξομοίωση σφαλμάτων SoCs με εκατομμύρια πύλες για εκατομμύρια κύκλους ρολογιού, χρησιμοποιώντας πολλαπλά μοντέλα σφαλμάτων και εξειδικευμένους λειτουργικούς εξομοιωτές. Εισάγουμε την πρώτη μέθοδο που δεν μεροληπτεί υπέρ κάποιου συγκεκριμένου μοντέλου σφαλμάτων. Η μέθοδος αυτή προσφέρει σύντομο χρόνο δημιουργίας προγραμμάτων ελέγχου, υπό αυστηρό περιορισμό στο χρόνο ελέγχου ορθής λειτουργίας και στο μέγεθος των προγραμμάτων ελέγχου. Τα προγράμματα ελέγχου αξιολογούνται από μία νέα αποδοτική πιθανοτική μέθοδο SBST, εκμεταλλευόμενη την αρχιτεκτονική του επεξεργαστή, καθώς και τη netlist του επεξεργαστή σε επίπεδο πυλών που έχει προκύψει από σύνθεση. Η προτεινόμενη μετρική που βασίζεται στα output deviations είναι πολύ γρήγορη καθώς δεν απαιτεί τη χρονοβόρα διαδικασία της εξομοίωσης σφαλμάτων και μπορεί να εφαρμοστεί σε οποιαδήποτε μέθοδο που βασίζεται στην τεχνική SBST.

Enabling Resist Processing Technologies for Advanced Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000830-000862 ◽  
Author(s):  
Antun Peic ◽  
Thorsten Matthias ◽  
Johanna Bartl ◽  
Paul Lindner
Keyword(s):  
Three Dimensional ◽  
Design Solution ◽  
Wafer Level ◽  
Coating Technology ◽  
3D Ic ◽  
Wafer Level Packaging ◽  
Aspect Ratios ◽  
Integration Schemes ◽  
Interconnect Design ◽  
Deep Cavities

The increasing adoption of advanced wafer-level packaging (WLP) technologies and high density interposer concepts clearly reflect the permanent need for form factor reduction, smaller process geometries and higher-count I/O on ICs. Currently, several strategies are being pursued to achieve these goals. The most promising approaches are summarized under the concept of three-dimensional integrated circuits (3D-IC) and three-dimensional wafer level packaging (3D-WLP) technology. A key component for 3D device integration schemes is the requirement of vertical through-silicon-via (TSV) interconnections that enables electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias. Despite the potential benefits associated with the integration of TSVs also significant challenges have to be overcome. One of the greatest challenges for present and even more for upcoming TSV design strategies still remains the processing of photoresist and other functional polymers at and within TSV geometries. To this day, it is still very difficult to achieve a conformal polymer coating in deep cavities, along steep side walls and especially within the extreme aspect ratios of TSV. Mainly this is due to the fact that standard surface coating methods such as spin coating were just not developed to meet the requirements posed by these high aspect ratio microstructures. New and innovative approaches are needed to meet these new challenges. Spray coating is one of the most promising technologies to overcome current barriers. However, even most of the available spray deposition equipment is facing its limits with steadily decreasing via diameters and increasing aspect ratios on the other hand. Successively, the multitude of these challenging technological developments in the 3D-IC and wafer-level packaging area has created the demand for innovative manufacturing approaches, new equipment and related tools. Herein we present our new EVG ®NanoSprayTM coating technology with unique capabilities to overcome the present limits of conformal resist coating over extreme topography. We demonstrate one particularly promising application for conformal polymer coatings; as an annular lining at the interface between the conducting metal filling in the TSV and the silicon wafer. The intrinsic properties of the polymer allow a TSV design solution that is more forgiving on coefficient of thermal expansion (CTE) mismatch-induced stress between the silicon substrate and the interfacing metal. Consequently, this new type of polymer buffered TSV interconnect design promises to significantly reduce thermal stress-induced TSV delamination as one of the dominant failure modes for 3-D interconnects. We further demonstrate the application of EVG ®NanoSprayTM as enabling coating technology for llithographic processing of conformal coated TSVs. The patterning of thin photoresist layers at the bottom of vias and along the steep sidewalls of deep cavities allows for more degrees of freedom in electrical contact formation. The presented EVG ®NanoSprayTM coating technology opens new dimensions in advanced wafer level packaging and provokes reconsidering prevailing limitations in interconnect design.

Advanced Anodic Bonding Processes For MEMS Applications

2003 ◽  
Vol 782 ◽  
Author(s):  
V. Dragoi ◽  
P. Lindner ◽  
T. Glinsner ◽  
M. Wimplinger ◽  
S. Farrens
Keyword(s):  
Three Dimensional ◽  
Anodic Bonding ◽  
Process Conditions ◽  
Wafer Level ◽  
Process Step ◽  
Packaging Process ◽  
Powerful Technique ◽  
Wafer Level Packaging ◽  
Single Process ◽  
Single Process Step

ABSTRACTAnodic bonding is a powerful technique used in MEMS manufacturing. This process is applied mainly for building three-dimensional structures for microfluidic applications or for wafer level packaging. Process conditions will be evaluated in present paper. An experimental solution for bonding three wafers in one single process step (“triple-stack bonding”) will be introduced.

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