scholarly journals One-chip analogue circuits for a new type of plasma wave receiver onboard space missions

2016 ◽  
Author(s):  
Takahiro Zushi ◽  
Hirotsugu Kojima ◽  
Hiroshi Yamakawa
Keyword(s):  
Plasma Wave ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Test System ◽  
Analog To Digital ◽  
Analogue Circuits ◽  
Application Specific Integrated Circuit ◽  
New Type ◽  
Asic Chip

Abstract. Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm x 1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.

scholarly journals One-chip analog circuits for a new type of plasma wave receiver on board space missions

2017 ◽  
Vol 6 (1) ◽  
pp. 159-167 ◽  
Author(s):  
Takahiro Zushi ◽  
Hirotsugu Kojima ◽  
Hiroshi Yamakawa
Keyword(s):  
Plasma Wave ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Dynamic Range ◽  
Test System ◽  
Analog To Digital ◽  
Application Specific Integrated Circuit ◽  
New Type ◽  
Narrow Dynamic Range ◽  
Asic Chip

Abstract. Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm  ×  1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz, respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.

scholarly journals Design of a BIST implemented AES crypto-processor ASIC

PLoS ONE ◽  
2021 ◽  
Vol 16 (11) ◽  
pp. e0259956
Author(s):  
Md. Liakot Ali ◽  
Md. Shazzatur Rahman ◽  
Fakir Sharif Hossain
Keyword(s):  
Integrated Circuit ◽  
Description Language ◽  
Industry Standard ◽  
The Usa ◽  
Application Specific Integrated Circuit ◽  
Hardware Description ◽  
Self Test ◽  
Asic Chip ◽  
Application Specific ◽  
Eda Tools

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

scholarly journals VMM - An ASIC for Micropattern Detectors

2018 ◽  
Vol 174 ◽  
pp. 07001 ◽  
Author(s):  
George Iakovidis
Keyword(s):  
Integrated Circuit ◽  
National Laboratory ◽  
Ball Grid Array ◽  
Brookhaven National Laboratory ◽  
Analog To Digital ◽  
Front End ◽  
Wide Range ◽  
Multiplexed Readout ◽  
Application Specific Integrated Circuit ◽  
Application Specific

The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

A COMMERCIAL OFF-THE-SHELF IMPLEMENTATION OF AN ANALOG NEURAL COMPUTER

2008 ◽  
Vol 17 (02) ◽  
pp. 241-258 ◽  
Author(s):  
SANJAY K. BODDHU ◽  
JOHN C. GALLAGHER ◽  
SARANYAN A. VIGRAHAM
Keyword(s):  
Differential Equation ◽  
Neural Networks ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Electrical Circuit ◽  
Embedded Control ◽  
Accuracy And Precision ◽  
Application Specific Integrated Circuit ◽  
Commercial Off The Shelf ◽  
Digital Simulations

For most applications, analog electrical circuit implementations of continuous-valued neural networks have been abandoned in favor of digital simulations. This is not surprising, as both precision and accuracy can be more easily ensured in digital computers. Still, because they use far fewer transistors and support components, analog circuits can still be orders of magnitude smaller than their digital simulations. In some application, like micro-robotics and embedded control, one might be willing to tolerate less accuracy and precision for the size and power benefits. One would not under any condition, however, tolerate significant behavioral mismatches between the differential equation and electrical circuit forms of the neural networks in question. In this paper, we will present a design for an analog neural computer that embodies the commonly used continuous time recurrent neural network. We will show that the computer possesses excellent behavioral congruence to the differential equation form even in the presence of significant practical compromises. We will also discuss the implications of this work for both practical Commercial, Off-The-Shelf (COTS) and Application-Specific Integrated Circuit (ASIC) devices.

scholarly journals The SALT—Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 107
Author(s):  
Carlos Abellan Abellan Beteta ◽  
Dimitra Andreou ◽  
Marina Artuso ◽  
Andy Beiter ◽  
Steven Blusk ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Pulse Shaping ◽  
Signal To Noise Ratio ◽  
Hadron Collider ◽  
Silicon Detector ◽  
Digital Signal ◽  
Analog To Digital ◽  
Lhcb Experiment ◽  
Application Specific Integrated Circuit ◽  
Application Specific

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

scholarly journals ANTIGONE: A Programmable Energy-Efficient Current Digitizer for an ISFET Wearable Sweat Sensing System

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2074
Author(s):  
Evgenia Voulgari ◽  
François Krummenacher ◽  
Maher Kayal
Keyword(s):  
Integrated Circuit ◽  
Energy Efficient ◽  
Dynamic Range ◽  
Field Effect Transistors ◽  
Frequency Converter ◽  
Sensor Data ◽  
Current Sensing ◽  
Analog To Digital ◽  
Sensing System ◽  
Front End

This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically designed to interface with multiple Ion-Sensitive Field-Effect Transistors (ISFETs) and detect biomarkers like pH, Na+, K+ and Ca2+ in human sweat. The ISFET-ASIC system can allow real-time noninvasive and continuous health monitoring. The ANTIGONE ASIC architecture is based on the current-to-frequency converter through the charge balancing principle. The same front-end can digitize multiple currents produced by four sweat ISFET sensors in time multiplexing. The front-end demonstrates good linearity over a dynamic range that spans from 1 pA up to 500 nA. The consumed energy per conversion is less than 1 J. The chip is programmable and works in eight different modes of operation. The system uses a standard Serial Peripheral Interface (SPI) to configure, control and read the digitally converted sensor data. The chip is controlled by a portable device over Bluetooth Low Energy (BLE) through a Microcontroller Unit (MCU). The sweat sensing system is part of a bigger wearable platform that exploits the convergence of multiparameter biosensors and environmental sensors for personalized and preventive healthcare.

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