Effect of Ni(P) Layer Thickness on Interface Reaction and Reliability of Ultrathin ENEPIG Surface Finish

Electroless Ni(P)/electroless Pd/immersion Au (ENEPIG) is a common surface finish in electronic packaging, while the Ni(P) layer increases the impedance of solder joints and leads to signal quality degradation in high-frequency circuits. Reducing the thickness of the Ni(P) layer can balance the high impedance and weldability. In this paper, the interfacial reaction process between ultrathin ENEPIG substrates with different Ni layer thicknesses (0.112 and 0.185 μm) and Sn–3.0Ag–0.5Cu (SAC305) solder during reflow and aging was studied. The bonding ability and reliability of solder joints with different surface finishes were evaluated based on solder ball shear test, drop test and temperature cycle test (TCT), and the failure mechanism was analyzed from the perspective of intermetallic compound (IMC) interface growth. The results showed that the Ni–Sn–P layer generated by ultrathin ENEPIG can inhibit the growth of brittle IMC so that the solder joints maintain high shear strength. Ultrathin ENEPIG with a Ni layer thickness of 0.185 μm had no failure cracks under thermal cycling and drop impact, which can meet actual reliability standards. Therefore, ultrathin ENEPIG has broad prospects and important significance in the field of high-frequency chip substrate design and manufacturing.

Performance Evaluation of Photovoltaic Modules by Combined Damp Heat and Temperature Cycle Test

Standard damp heat (DH), temperature cycle (TC), and combined DH-TC tests were performed using monocrystalline Si 72-cell modules with a conventional ethylene vinyl acetate (EVA) encapsulant, and their module performance and electroluminescence images were investigated. During the DH test, a significant drop (~20%) in the maximum output power of the module was noticed, primarily because of the degradation of fill factor and an increase in series resistance at 5500 h of DH testing (DH5500), presumably due to the corrosion of metal electrodes by moisture ingress. Conversely, it was revealed that temperature cycling did not seriously degrade module performance until 1400 cycles. However, the combined DH5000-TC600 test suggested in this study, with a sequence of DH1000-TC200-DH1000-TC200-DH1000-TC200-DH2000, was confirmed to provide harsher conditions than the DH-only test by causing a 20% decrease in maximum output power (Pmax) after DH3000/TC400. Promisingly, we confirmed that the module with a polyolefin elastomer encapsulant showed better durability than the module with EVA even in the combined DH-TC test, showing a limited decrease in Pmax (~10%) even after the DH5500/TC600 test.

Development of thin package using the glass carrier substrate

“The glass carrier substrate” formed on support glass using conventional build-up substrate technologies is developed. This substrate is ultrathin, and is suitable for the applications that thinner packages are highly demanded, such as for mobiles. The advantage of glass as the carrier for the substrate is that the CTE of glass is close to that of silicon. The CTE matching of glass with silicon enables the narrow pitch mounting, because of reduced distortions between the chip and the substrate. When the chip is bonded on the substrate, glass is still combined with the substrate as the carrier. After chip bonding, the substrate can easily peeled off with laser irradiating through glass due to the characters of adhesive layer. To verify the advantage, we prepared the thin substrate and made a connection with a narrow pitch (50um) bump chip, by means of Thermal Compression Bonding with non-conductive paste. The process of injection molding was used for packaging the substrate. We evaluated the reliability of the thin package, by temperature cycle test (JEDEC MSL-3+Cond.B). It was confirmed that the package passed the criteria. It is convinced that the package with glass carrier substrate is an effective solution for making thinner packages.

TCT Reliability of Organic Passivation Layer for WLCSP

Wafer level chip scale packages (WLCSP) have been increasingly used in portable electronic products such as mobile phones. Solder bumps with redistribution layer (RDL) are typical interconnect technology for WLCSP applications. One of the major concerns in joint reliability is the failure by temperature cyclic stresses. In addition, in terms of heat tolerance or device yields, process temperature of RDL dielectric is limited around 200deg.C in some packaging applications. According to our board level reliability test for temperature cycle test (TCT), photosensitive polyimide (PI) which is 200deg.C curable material has lower fail rate than polybenzoxazole (PBO) by TCT. In this study, we compared the actual board level test and Finite Element Analysis (FEA) during temperature cycle test, and correlated the mechanical and fatigue properties of passivation layer material with TCT reliability.

Comparison Study on Friction-Welded Cu-Al Material and Pure Cu/Al

Friction-weld Cu-Al has many potential applications to replace the traditional Cu or Al conductor as it has the superior performance and low cost. For ensuring the reliability of Al/Cu metal joints, the mechanical, electrical and long-term properties were investigated by comparing the properties of Cu and Al. The results show that the mechanical properties (tension, impact and hardness) of friction-welded Cu-Al are between the values of Cu and Al, and the welding seam is not the weakest part in mechanical. The electrical resistance of Cu-Al is also between the values of Cu and Al, and does not increase after long-term vibration test and high-low temperature cycle test. The welding seaming is a weak part for salt spray test, it is better to be protected for use.