TCT Reliability of Organic Passivation Layer for WLCSP

2015 ◽  
Vol 2015 (1) ◽  
pp. 000505-000509 ◽  
Author(s):  
Mitsuru Fujita ◽  
Atsushi Fujii ◽  
Shuji Shimoda ◽  
Yoshiharu Kariya
Keyword(s):  
Passivation Layer ◽  
Fatigue Properties ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Element Analysis ◽  
Joint Reliability ◽  
Solder Bumps ◽  
Temperature Cycle Test ◽  
Board Level ◽  
Interconnect Technology

Wafer level chip scale packages (WLCSP) have been increasingly used in portable electronic products such as mobile phones. Solder bumps with redistribution layer (RDL) are typical interconnect technology for WLCSP applications. One of the major concerns in joint reliability is the failure by temperature cyclic stresses. In addition, in terms of heat tolerance or device yields, process temperature of RDL dielectric is limited around 200deg.C in some packaging applications. According to our board level reliability test for temperature cycle test (TCT), photosensitive polyimide (PI) which is 200deg.C curable material has lower fail rate than polybenzoxazole (PBO) by TCT. In this study, we compared the actual board level test and Finite Element Analysis (FEA) during temperature cycle test, and correlated the mechanical and fatigue properties of passivation layer material with TCT reliability.

scholarly journals Improving the Solder Joint Reliability of a Power Leadframe Package Using Thermomechanical Simulation

2019 ◽  
pp. 1-6
Author(s):  
Jefferson Talledo
Keyword(s):  
Solder Joint ◽  
Heat Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Mold Material ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Thermomechanical Simulation ◽  
Board Level

Leadframe-based packages are commonly used for semiconductor power devices. With these packages, heat dissipation is much better compared with laminate substrated-based packages. However, the solder joint reliability requirement under thermal cycling condition is also higher and this is what makes the development of a power package challenging. One of the usual requirements from customers is that there should be no solder joint failure up to 2,000 thermal cycles. This paper presents the thermomechanical simulation of a power leadframe package that was conducted to improve its solder joint reliability. Board level solder joint cycle life was predicted using finite element analysis and the result was validated with actual solder life result from board level reliability evaluation. Since available solder prediction equation was for the characteristic life (63.2% accumulative failure), using the normalized characteristic life was implemented for predicting the number of cycles to first failure of the solder joint connection and the approach showed good agreement with the actual result. Results also indicated that the choice of epoxy mold material and the type of PCB (printed circuit board) have a significant contribution to the solder joint reliability performance.

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

2008 ◽  
Vol 48 (4) ◽  
pp. 602-610 ◽  
Author(s):  
Xiaowu Zhang ◽  
Vaidyanathan Kripesh ◽  
T.C. Chai ◽  
Teck Chun Tan ◽  
D. Pinjala
Keyword(s):  
Solder Joint ◽  
Reliability Analysis ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Board Level ◽  
Wafer Level Package

Low Profile and Large Size WLCSP in IoT Applications

2019 ◽  
Vol 2019 (1) ◽  
pp. 000327-000332
Author(s):  
Tom Tang ◽  
Kuei Hsiao Kuo ◽  
Victor Lin ◽  
Kelly Chen ◽  
J.Y. Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Wafer Level ◽  
Joint Reliability ◽  
Large Size ◽  
Low Profile ◽  
Chip Scale Package ◽  
Iot Devices ◽  
Small Form Factor ◽  
Board Level ◽  
Board Level Reliability

Abstract Recently, Wafer Level Chip Scale Package (WLCSP) Package is being rapidly adopted in Internet of Things (IoT) and consumer mobile electronics due to its low profile, small form factor and relatively easy assembly process. WLCSP with large die size becomes the trend in fulfilling high performance product demands. However, the solder joint reliability performances of WLCSP is the key challenge and becomes critical as increasing die size, especially the size is larger than 6 × 6 mm2. There is also growing interest in low profile WLCSP packages to less than 300 microns, especially when they are placed in a limited space inside IoT devices. Thin wafers are fragile and must be supported over their full dimensions to prevent cracking and breakage. An increasingly popular approach to thin wafer handling involves grinding and taping thin wafers with in-line machines. A specific carry tape have been also developed for transferring thin wafers after thinning. In this paper, WLCSP board level reliability for both large die size and low profile was studied, a test vehicle used for the large WLCSP package testing has 350um ball pitch and fully populated array. In addition to board level reliability test simulation and data collection, processing challenges were discussed, as well as processing solutions for thin wafer handling.

Board Level Reliability Enhancement for A Double-bump Wafer Level Chip Scale Package

2004 ◽  
Vol 1 (2) ◽  
pp. 64-71 ◽  
Author(s):  
Xiaowu Zhang ◽  
E. H. Wong ◽  
Mahadevan K. Iyer
Keyword(s):  
Solder Joint ◽  
Design Guidelines ◽  
Wafer Level ◽  
Element Analysis ◽  
Chip Scale Package ◽  
Form Design ◽  
Parametric Studies ◽  
Reliability Enhancement ◽  
Board Level ◽  
Board Level Reliability

This paper presents a nonlinear finite element analysis on board level solder joint reliability enhancement of a double-bump wafer level chip scale package (CSP). A viscoplastic constitutive relation is adopted for the solders to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation, which has been verified by experimental results using one of the double-bump wafer level CSP packages as the test vehicle. A series of parametric studies were performed by changing the Sn/Ag inner bump size (UBM pad size and standoff height), the eutectic Sn/Pb external solder joint size (pad size and standoff height), pitch, die thickness, and the encapsulant thickness. The results obtained from the modeling are useful to form design guidelines for board level reliability enhancement of the wafer level CSP packages.

Design and Reliability Analysis of Wafer Level Package With Bubble-Like Buffer Layer

2003 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Solder Joint ◽  
Buffer Layer ◽  
Chip Thickness ◽  
Buffer Layers ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Compliant Layer ◽  
Wafer Level Package

In order to enhance the wafer level package (WLP, Figure 1) reliability for larger chip size, many different kinds of WLP have been adopted, all have a compliant layer under the pads have to relieve the thermal stress of the solder joint. Usually, the solder joint reliability is enhanced with the increase of the thickness of the compliant layer. However, the fabrication processes of the WLP restrict the thickness of the compliant layer. With that in mind this research proposed a novel WLP package with bubble-like buffer layer (Figure 2) which is composed of a bubble-like plate and a buffer layer between the chip and the solder joint. The main goal of this research was to study the effects of the geometric dimensions and material properties of the bubble-like layer on the reliability of the WLP. For the parametric analysis purpose, a 2-D nonlinear finite element analysis for the proposed WLP was conducted. The results revealed that both the bubble-like plate and the buffer layer provide excellent compliant effects. However, the buffer layer has a more significant effect on enhancing the solder joint reliability. Also, for a WLP with buffer structure, the effect of the chip thickness on the reliability could be significantly reduced. In addition, the difference between the filled and non-filled buffer layers also affected the reliability of the solder joint. The results revealed that the WLP with the buffer layer and the no-fill bubble-like plate had the better reliability.

Reliability of Multi-Layer Wiring Board Embedded with Two Dies in Stacked Configuration

2014 ◽  
Vol 2014 (1) ◽  
pp. 000161-000164 ◽  
Author(s):  
Koji Munakata ◽  
Nobuki Ueta ◽  
Masahiro Okamoto ◽  
Kumi Onodera ◽  
Kazu Itoi ◽  
...  
Keyword(s):  
Stress Test ◽  
Base Material ◽  
Single Step ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Level 3 ◽  
Semiconductor Packages ◽  
Wiring Board ◽  
Temperature Cycle Test ◽  
Electrical Connections

As electronic devices decrease in size and increase in functionality, their surface-mount components grow in number. This trend created a need for securing appropriate space in and on a wiring board to accommodate necessary components. Conventionally, dies are mounted on a wiring board. Much effort is spent for space savings. We have come up with a structure to include dies inside a wiring board and succeeded in fabricating the board in which two dies are embedded in a 3D stacked configuration. This new structure shrinks the foot print size and thus contributes to higher density and functionality of a semiconductor package and SiP. In addition, since the base material is polyimide, this board is as thin as 0.45 mm with two WLP (Wafer Level Package) dies (3 mm x 3 mm x 0.085 mm) embedded between any of 9 wiring layers. The module level warpage on the both sides of this board is 0.035 mm, so it is possible to mount components on the both sides. This board was fabricated based on our WABE technologyTM (Wafer and Board level Embedding technology) that includes a single step co-laminating process and embedded technology using conductive-paste-filled vias for establishing z-axis interlayer electrical connections. The conductive paste formed intermetallic compound with the copper foil and the via showed stable electrical connections by metallic bonding. Copper pads were fabricated on the dies by a wafer level process in advance. The polyimide-based films were laminated with adhesive and the dies were embedded. At the same time, electrical connections were established. This method enables the production of an embedded board by one-time curing after the alignment and fixing of necessary layers. We applied this method to the new structure that includes two dies in a 3D configuration to achieve a simple fabrication process using the single step co-lamination process. We evaluated the reliability of this board as below. The electric resistance was measured after various reliability tests including Temperature Cycle Test, Temperature Humidity Bias Test and Highly Accelerated Stress Test following a moisture sensitive reflow test (based on IPC/JEDEC J-STD-020 Level 3). From the results, there were no major defects observed in the test boards, either visually or functionally. This two-die embedding technology helps to realize the miniaturization and contribute to higher functionality of semiconductor packages and SiPs.

Reliability Analysis of WLCSP Using Tie-Release Crack Prediction Finite Element Technique

2005 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Fatigue Life ◽  
Solder Joint ◽  
Solder Joints ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Prediction Technique ◽  
Packaging Structure

For the purpose of enhancing the solder joint reliability of a wafer level chip scaling package (WLCSP), the WLCSP adopted the familiar design structure where both the stress compliant layer with low elastic modulus and the dummy solder joints are considered as structural supports. However, the predicted fatigue life of the solder joints at the internal part of the packaging structure using the conventional procedures of finite element simulation are higher than under actual conditions as a result of the perfect bonding assumption in the modeling. In this research, in order to improve the thermo-mechanical reliability of the solder joints, a node tie-release crack prediction technique, based on non-linear finite element analysis (FEA), is developed and compared with the estimation of the solder joint reliability using conventional methodology. The predicted results of reliability, using the novel prediction technique, show a lower fatigue life of the solder joint than that when using conventional one when the fracture regions in the dummy solder joints are simulated under quasi-steady state. At the same time, the result of the thermal cycling test also shows good agreement with the simulated result when using the proposed node tie-release crack prediction analysis.

A Study on Reliability of High-Temperature Joint in Packaging Structure

2011 ◽  
Author(s):  
Takayuki Ishikawa ◽  
Toshikazu Oshidari ◽  
Hiromi Sugihara ◽  
Qiang Yu
Keyword(s):  
High Temperature ◽  
Cooling System ◽  
High Reliability ◽  
Pure Aluminum ◽  
Bending Test ◽  
Temperature Cycle ◽  
Element Analysis ◽  
Operative Temperature ◽  
Temperature Cycle Test ◽  
Packaging Structure

In recent years, the research and development of hybrid cars and electrical vehicles become one of the top targets. High electric power is necessary for those cars to run in motor drive, and power devices such as inverter are employed for the control. Since operative temperature of Si power device is from −40 to 150°C level, a big cooling system is needed to control the temperature lower than 150°C. Recently the SiC chip had been developed to downsize the cooling system and reduce the loss of energy, because the operative temperature of SiC chip can be increased to over 300°C. However mounting method that can be used at high temperature environment is not established yet. The author’s group has proposed a new mounting method using Ag-Nano material to mount the SiC chip on a metal board. In existing mounting method, stress was relieved by transformation of comparatively soft solder region. Thus, in the new method, the junction Ag-Nano is too hard to relax the stress. So stress relaxation facility is given to the pure aluminum substrate side. In addition, jointing Ag-Nano on aluminum board is not possible, enabled by Ag and Ni plating on substrate. And these films prevent aluminum board from oxidizing. This mounting method achieves low temperature mounting and high reliability in thermal cycle. In this study, reliability of Ni plating was investigated because it was brought out that Ni plating becomes as a new weak point during high temperature cycle test ranged from −40 to 300°C. Mechanical properties of Ni plating were investigated first. Test specimens with plating and without plating for four point bending test were prepared to compare the difference. And stress-strain relation of plating was evaluated. In addition, fatigue strength was investigated by cyclic bending test. With these material properties, fatigue life of Ni plating in packaging structure was evaluated by finite-element-analysis. And optimum dimension of the structure was studied.

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