DEVELOPMENT OF MULTILAYER TEXTILE STRUCTURES FOR FILTERING APPLICATIONS – A NEW SURGICAL MASK APPROACH

Universal mask use has emerged as one of the main strategies for reducing community transmission of the SARS-COV-2 virus. Due to the scarcity of material to produce disposable surgical masks, the governmental strategy was oriented to the community masks, even though performance levels were still not the same. This study intended to develop a new generation of surgical masks with different warp knit structures, evaluating the potential of multilayer gradient performance. The assembling methodology was also considered by modifying flat-bed calendering process parameters and manipulating final structures into a new origami design concept, and the overall mask filtration performance was reviewed. The overlapping of monolayers increased the substrate resistance to air and water vapour permeability, also influencing the water molecule's adhesion. The introduction of the web allowed a better layer assembling during the flat-bad process. Moreover, the breathability and water vapour diffusion are compromised since the adhesive web with temperature tends to merge and occupy the empty spaces between the layers. Moving forward, calendared structures without a web proved to be the best approach, meeting the certification criteria for surgical masks level I and II.

The Waffle Substrate: A Novel Approach to Reducing Substrate Resistance in SiC Power Devices

Silicon carbide (SiC) is enabling the next generation of semiconductor power devices, with performance orders-of-magnitude beyond silicon. The most important power switching device is the SiC power MOSFET, whose performance is limited by three main resistance elements: the channel, drift layer, and substrate. For blocking voltages in the range of 400-900V, substrate resistance is a major limitation. Wafer thinning is currently used to reduce the substrate resistance, but this also reduces the strength of the wafers. We report on a waffle substrate technique that relies on wafer thinning and inductively coupled plasma (ICP) etching to reduce the substrate resistance below levels achievable by thinning alone, while retaining the mechanical stability of a moderately-thinned substrate. This technique can be applied to any SiC device for which substrate resistance is a limitation.

Simulation-Based Sensitivity Analysis of Conduction and Switching Losses for Silicon Carbide Power MOSFETs

The behavior of silicon carbide power MOSFETs is analyzed using TCAD device simulations with respect to conduction and switching losses. Device designs with varying breakdown voltages are simulated. The contributions to the on-state resistance are shown at room and elevated temperature. Whereas channel and substrate resistance dominate at low breakdown voltages, drift and JFET resistance dominate at high breakdown voltages. With increasing temperature, the channel resistance decreases and thus the drift resistance is the main contributor already at medium breakdown voltages. Manufacturing processes of a device can have a high influence on its losses. Variations in interface mobility, drift doping, and p-body doping can lead to a significant change of on-resistance, internal capacitances, and reverse recovery charge. For higher voltage classes the drift layer properties should be of major interest as it influences on-resistance and reverse recovery charge.

Ohmic Curing of Three-Dimensional Printed Silver Interconnects for Structural Electronics

Ohmic curing was utilized as a method to improve the conductivity of three-dimensional (3D) interconnects printed from silver-loaded conductive inks and pastes. The goal was to increase conductivity of the conductive path without inducing damage to the substrate. The 3D via/interconnect structure was routed within 3D polymeric substrates and had external and internal sections. The 3D structures were created by the additive manufacturing (AM) process of stereolithography (SL) and were designed to replicate manufacturing situations which are common in the fabrication of 3D structural electronics that involve a combination of AM and direct write (DW) processing steps. The photocurable resins the 3D substrates were made of possessed glass transition temperatures of 75 °C and 42 °C meaning that a nonthermal method to increase the conductivity of the printed traces was needed as the conductive inks tested in this study required oven cure temperatures greater than 100 °C to perform properly. Ohmic curing was shown to decrease the measured resistance of the via/interconnect structure without harming the substrate. Substrate damage was observed on thermally cured samples and was characterized by discoloration and scaling of the substrate. Resistance measurements of the via/interconnect structures revealed samples cured by the ohmic curing process performed equal or better than samples subjected to thermal curing. The work presented here demonstrates a method to overcome the thermal cure temperature limitations of polymeric substrates imposed on the processing parameters of conductive inks during the fabrication of 3D structural electronics and presents an example of overcoming a manufacturing process problem associated with this emerging technology. An ink selection process involving characterization of the compatibility of inks with the substrate material and the use of different inks for the via and interconnect sections was also discussed.