Correlation between Package-Level High-Speed Solder Ball Shear/Pull and Board-Level Mechanical Drop Tests with Brittle Fracture Failure Mode, Strength, and Energy

Author(s):  
Fubin Song ◽  
S. W. Ricky Lee ◽  
Keith Newman ◽  
Bob Sykes ◽  
Stephen Clark
Author(s):  
C.H. Zhong ◽  
Sung Yi

Abstract Ball shear forces of plastic ball grid array (PBGA) packages are found to decrease after reliability test. Packages with different ball pad metallurgy form different intermetallic compounds (IMC) thus ball shear forces and failure modes are different. The characteristic and dynamic process of IMC formed are decided by ball pad metallurgy which includes Ni barrier layer and Au layer thickness. Solder ball composition also affects IMC formation dynamic process. There is basically no difference in ball shear force and failure mode for packages with different under ball pad metallurgy before reliability test. However shear force decreased and failure mode changed after reliability test, especially when packages exposed to high temperature. Major difference in ball shear force and failure mode was found for ball pad metallurgy of Ni barrier layer including Ni-P, pure Ni and Ni-Co. Solder ball composition was found to affect the IMC formation rate.


2009 ◽  
Vol 38 (6) ◽  
pp. 884-895 ◽  
Author(s):  
E.H. Wong ◽  
S.K.W. Seah ◽  
C.S. Selvanayagam ◽  
R. Rajoo ◽  
W.D. van Driel ◽  
...  

Author(s):  
Nikhil Lakhkar ◽  
Puligandla Viswanadham ◽  
Dereje Agonafer

Ball shear testing is typically conducted in Wafer level chip scale package (WLCSP) fabrication to estimate the strength of the solder ball attachment. Generally, the solder ball shear strength is dependent on the solder ball size, pad size, solder/pad interface treatment, reflow temperature and time. Solder ball strength is also a function of ram speed and height at which the ball is sheared with respect to the wafer. Recent investigations suggest that ball shear test is being used as an indicator for board level reliability of assemblies. In current market lead time for launching a new product is very short. Unfortunately, it takes several weeks to qualify a new product by board level qualification process. If there is a methodology through which one can predict the board level performance by extrapolating the wafer level test, it will save great amount of resources in testing and millions of dollars worth of testing time. In the first part of this study, we conducted a wafer level ball shear test. A DOE was created for varying wafer level structural parameters like solder ball size and type. Ball shear tests and Accelerated thermal cycling have similar failure signatures of compression on inner side and tension on outer side. Thus, for specific cases there is a possibility of correlating the two failure methodologies based on their failure signatures. Strain rate for ball shear test was determined based on shear speed and solder pad diameter. Strain rate for accelerated thermal cycling was determined based on difference in CTE between board and package. In this paper, results from ball shear test and accelerated thermal cycling are compared to find correlations for specific cases. The correlations derived from this study are statistical and empirical.


2007 ◽  
Vol 4 (4) ◽  
pp. 186-194 ◽  
Author(s):  
C.I. Chen ◽  
S.C. Wu ◽  
D.S. Liu ◽  
C.Y. Ni ◽  
T. D. Yuan

Due to the high speed and high I/O count requirements for semiconductor packages, thousands of soldered interconnections are indispensable, and this situation renders traditional finite element method (FEM) analysis a formidable challenge. This paper presents a 3D-equivalent global model and local submodeling technique to investigate board-level solder joint reliability under cyclic temperature loading. The equivalent global model is capable of addressing critical solder failure locations. An individual local solder ball is used to predict the number of cycles to failure. The high performance flip-chip ball grid array (HFCBGA) package case was studied with the provided experimental data. According to FEM results, the predicted solder ball life is close to that observed experimentally. Therefore, the global-to-local modeling technique can be concluded to provide an efficient methodology for evaluating very high pin count HFCBGA package reliability.


Author(s):  
Greg M. Heaslip ◽  
Jeff M. Punch ◽  
Bryan A. Rodgers ◽  
Claire Ryan

There is considerable reported evidence that a large percentage of failures which afflict portable electronic products are due to impact or shock during use. Failures of the external housing, internal electronic components, package-to-board interconnects, and liquid crystal display panels may occur as the result of accidental drops. Moreover, the introduction of lead-free solder to the electronics industry will bring additional design implications for future generations of mobile information and communication technology (ICT) applications. In this paper, drop tests performed on printed circuit boards (PCBs) populated with ball grid arrays (BGAs) are reported. During testing, measurements from strain gages were recorded using a high-speed data acquisition system. Electrical continuity through each package was monitored during the impact event in order to detect failure of package-to-board interconnects. Life distributions were established for both lead-free and eutectic solders for various drop heights. Microsections of the failed interconnects were obtained to determine the failure mechanisms for a range of drop heights. The life test data presented in this paper suggests that for board level drop testing different failure mechanisms can occur at different stress levels and that there is a considerable difference between lead-free solder characteristic life and tin-lead (SAC) solder characteristic life.


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