Single-Crystal C60Needle/CuPc Nanoparticle Double Floating-Gate for Low-Voltage Organic Transistors Based Non-Volatile Memory Devices

Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.

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Resistive switching characteristics of all-solution-based Ag/TiO2/Mo-doped In2O3devices for non-volatile memory applications

Journal of Materials Chemistry C ◽

10.1039/c6tc03607d ◽

2016 ◽

Vol 4 (46) ◽

pp. 10967-10972 ◽

Cited By ~ 35

Author(s):

Sujaya Kumar Vishwanath ◽

Jihoon Kim

Keyword(s):

Resistive Switching ◽

Retention Time ◽

Elevated Temperatures ◽

Switching Behavior ◽

Memory Devices ◽

Bipolar Switching ◽

Non Volatile Memory ◽

Volatile Memory ◽

Switching Characteristics ◽

Memory Applications

The all-solution-based memory devices demonstrated excellent bipolar switching behavior with a high resistive switching ratio of 103, excellent endurance of more than 1000 cycles, stable retention time greater than 104s at elevated temperatures, and fast programming speed of 250 ns.

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Lead based ferroelectric capacitors for low voltage non-volatile memory applications

Integrated Ferroelectrics ◽

10.1080/10584589808012702 ◽

1998 ◽

Vol 19 (1-4) ◽

pp. 159-177 ◽

Cited By ~ 5

Author(s):

S. Aggarwal ◽

A. S. Prakash ◽

T. K. Song ◽

S. Sadashivan ◽

A. M. Dhote ◽

...

Keyword(s):

Low Voltage ◽

Non Volatile Memory ◽

Volatile Memory ◽

Memory Applications ◽

Ferroelectric Capacitors

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Semiconductor Nanocrystal Floating-gate Memory Devices

MRS Proceedings ◽

10.1557/proc-830-d5.1 ◽

2004 ◽

Vol 830 ◽

Cited By ~ 5

Author(s):

P. Dimitrakis ◽

P. Normand

Keyword(s):

Low Voltage ◽

Ion Beam ◽

Low Energy ◽

Floating Gate ◽

Device Performance ◽

Memory Devices ◽

Research Directions ◽

Semiconductor Nanocrystal ◽

Floating Gate Memory ◽

Attractive Option

ABSTRACTCurrent research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.

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Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156420400017 ◽

2020 ◽

Vol 29 (01n04) ◽

pp. 2040001

Author(s):

N. R. Butterfield ◽

R. Mays ◽

B. Khan ◽

R. Gudlavalleti ◽

F. C. Jain

Keyword(s):

Quantum Dot ◽

Hafnium Oxide ◽

Experimental Testing ◽

Memory Cell ◽

Floating Gate ◽

Carrier Injection ◽

High K ◽

Non Volatile Memory ◽

Volatile Memory ◽

High K Dielectric

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

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