Differential delay aware instantaneous recovery scheme with traffic splitting

2015 ◽  
Vol 30 (5) ◽  
pp. e3075 ◽  
Author(s):  
Abu Hena Al Muktadir ◽  
Eiji Oki
2012 ◽  
Vol 1 (1) ◽  
pp. 28-32 ◽  
Author(s):  
Agostinho Antonio Jose ◽  
Abu Hena Al Muktadir ◽  
Eiji Oki

2009 ◽  
Vol E92-B (3) ◽  
pp. 909-921
Author(s):  
Depeng JIN ◽  
Wentao CHEN ◽  
Li SU ◽  
Yong LI ◽  
Lieguang ZENG

2013 ◽  
Vol E96.B (12) ◽  
pp. 3116-3123
Author(s):  
Zhiheng ZHOU ◽  
Liang ZHOU ◽  
Shengqiang LI

2015 ◽  
Vol E98.C (4) ◽  
pp. 333-339 ◽  
Author(s):  
Go MATSUKAWA ◽  
Yohei NAKATA ◽  
Yasuo SUGURE ◽  
Shigeru OHO ◽  
Yuta KIMI ◽  
...  

1988 ◽  
Vol 24 (21) ◽  
pp. 1305 ◽  
Author(s):  
C.A. Wade ◽  
A.D. Kersey ◽  
A. Dandridge

Author(s):  
Wladimir De la Cadena ◽  
Asya Mitseva ◽  
Jens Hiller ◽  
Jan Pennekamp ◽  
Sebastian Reuter ◽  
...  
Keyword(s):  

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 188
Author(s):  
Žiga Korošak ◽  
Nejc Suhadolnik ◽  
Anton Pleteršek

The aim of this work is to tackle the problem of modulation wave shaping in the field of near field communication (NFC) radio frequency identification (RFID). For this purpose, a high-efficiency transmitter circuit was developed to comply with the strict requirements of the newest EMVCo and NFC Forum specifications for pulse shapes. The proposed circuit uses an outphasing modulator that is based on a digital-to-time converter (DTC). The DTC based outphasing modulator supports amplitude shift keying (ASK) modulation, operates at four times the 13.56 MHz carrier frequency and is made fully differential in order to remove the parasitic phase modulation components. The accompanying transmitter logic includes lookup tables with programmable modulation pulse wave shapes. The modulator solution uses a 64-cell tapped current controlled fully differential delay locked loop (DLL), which produces a 360° delay at 54.24 MHz, and a glitch-free multiplexor to select the individual taps. The outphased output from the modulator is mixed to create an RF pulse width modulated (PWM) output, which drives the antenna. Additionally, this implementation is fully compatible with D-class amplifiers enabling high efficiency. A test circuit of the proposed differential multi-standard reader’s transmitter was simulated in 40 nm CMOS technology. Stricter pulse shape requirements were easily satisfied, while achieving an output linearity of 0.2 bits and maximum power consumption under 7.5 mW.


Sign in / Sign up

Export Citation Format

Share Document