scholarly journals Hardware Acceleration of the Tate Pairing in Characteristic Three

2005 ◽  
pp. 398-411 ◽  
Author(s):  
P. Grabher ◽  
D. Page
Keyword(s):  
Hardware Acceleration ◽  
Tate Pairing

Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve

2007 ◽  
Vol 53 (2-3) ◽  
pp. 85-98 ◽  
Author(s):  
Robert Ronan ◽  
Colm ó hÉigeartaigh ◽  
Colin Murphy ◽  
Michael Scott ◽  
Tim Kerins
Keyword(s):  
Hyperelliptic Curve ◽  
Hardware Acceleration ◽  
Tate Pairing ◽  
Genus 2

Hardware Acceleration of Bilateral Filters

2013 ◽  
Vol 133 (2) ◽  
pp. 132-138
Author(s):  
Shuhei Isa ◽  
Chikatoshi Yamada ◽  
Yasunori Nagata
Keyword(s):  
Hardware Acceleration ◽  
Bilateral Filters

The real-time computing of the Stirling formula based on hardware acceleration

2013 ◽  
Author(s):  
Jiyang Yu ◽  
Dan Huang ◽  
Siyang Zhao ◽  
Nan Pei ◽  
Huixia Cheng ◽  
...  
Keyword(s):  
Real Time ◽  
Hardware Acceleration ◽  
Stirling Formula ◽  
The Real ◽  
Real Time Computing

Design and implementation of matrix hardware acceleration based on FPGA/Nios-Ⅱ

2011 ◽  
Vol 25 (4) ◽  
pp. 377-383 ◽  
Author(s):  
Fang Xu ◽  
Yi Xi ◽  
Hong Chen ◽  
Weiwei Jin
Keyword(s):  
Hardware Acceleration ◽  
Design And Implementation

Design and Implementation of Low Energy Wireless Network Nodes based on Hardware Compression Acceleration

2019 ◽  
Vol 12 ◽  
Author(s):  
Hui Yang ◽  
Anand Nayyar
Keyword(s):  
Energy Consumption ◽  
Data Compression ◽  
Energy Saving ◽  
Optimization Design ◽  
Hardware Acceleration ◽  
Transmission Efficiency ◽  
General Purpose ◽  
Storage Space ◽  
General Purpose Processor ◽  
Compression Time

: In the fast development of information, the information data is increasing in geometric multiples, and the speed of information transmission and storage space are required to be higher. In order to reduce the use of storage space and further improve the transmission efficiency of data, data need to be compressed. processing. In the process of data compression, it is very important to ensure the lossless nature of data, and lossless data compression algorithms appear. The gradual optimization design of the algorithm can often achieve the energy-saving optimization of data compression. Similarly, The effect of energy saving can also be obtained by improving the hardware structure of node. In this paper, a new structure is designed for sensor node, which adopts hardware acceleration, and the data compression module is separated from the node microprocessor.On the basis of the ASIC design of the algorithm, by introducing hardware acceleration, the energy consumption of the compressed data was successfully reduced, and the proportion of energy consumption and compression time saved by the general-purpose processor was as high as 98.4 % and 95.8 %, respectively. It greatly reduces the compression time and energy consumption.

Accelerating Genomic Data Analytics with Composable Hardware Acceleration Framework

IEEE Micro ◽  
2021 ◽  
pp. 1-1
Author(s):  
Tae Jun Ham ◽  
David Bruns-Smith ◽  
Brendan Sweeney ◽  
Yejin Lee ◽  
Seong Hoon Seo ◽  
...  
Keyword(s):  
Data Analytics ◽  
Genomic Data ◽  
Hardware Acceleration

High-Performance Image Filters via Sparse Approximations

2020 ◽  
Vol 3 (2) ◽  
pp. 1-19
Author(s):  
Kersten Schuster ◽  
Philip Trettner ◽  
Leif Kobbelt
Keyword(s):  
High Performance ◽  
Hardware Acceleration ◽  
Optimization Method ◽  
Translation Invariant ◽  
Approximation Quality ◽  
Trade Offs ◽  
Sparse Approximations ◽  
Image Filters ◽  
Good Trade ◽  
And Performance

We present a numerical optimization method to find highly efficient (sparse) approximations for convolutional image filters. Using a modified parallel tempering approach, we solve a constrained optimization that maximizes approximation quality while strictly staying within a user-prescribed performance budget. The results are multi-pass filters where each pass computes a weighted sum of bilinearly interpolated sparse image samples, exploiting hardware acceleration on the GPU. We systematically decompose the target filter into a series of sparse convolutions, trying to find good trade-offs between approximation quality and performance. Since our sparse filters are linear and translation-invariant, they do not exhibit the aliasing and temporal coherence issues that often appear in filters working on image pyramids. We show several applications, ranging from simple Gaussian or box blurs to the emulation of sophisticated Bokeh effects with user-provided masks. Our filters achieve high performance as well as high quality, often providing significant speed-up at acceptable quality even for separable filters. The optimized filters can be baked into shaders and used as a drop-in replacement for filtering tasks in image processing or rendering pipelines.

scholarly journals Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 73
Author(s):  
Francesco Ratto ◽  
Tiziana Fanni ◽  
Luigi Raffo ◽  
Carlo Sau
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Systems Design ◽  
Hardware Acceleration ◽  
High Level Synthesis ◽  
Clock Gating ◽  
Technology Application ◽  
Positive Effects ◽  
High Level ◽  
Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

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