Low-Voltage Power-Efficient Amplifiers for Emerging Applications

2008 ◽  
pp. 147-165 ◽  
Author(s):  
A. López-Martin ◽  
R.G. Carvajal ◽  
E. López-Morillo ◽  
L. Acosta ◽  
T. S´nchez-Rodriguez ◽  
...  
Keyword(s):  
Low Voltage ◽  
Power Efficient

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

Common Mode Feedback Circuits for Low Voltage Fully-Differential Amplifiers

2016 ◽  
Vol 25 (10) ◽  
pp. 1650124 ◽  
Author(s):  
S. Rekha ◽  
T. Laxminidhi
Keyword(s):  
Power Supply ◽  
Continuous Time ◽  
Efficient Solution ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Power Efficient ◽  
Differential Amplifiers ◽  
Fully Differential ◽  
Simulation Results

Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5[Formula: see text]V in 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1[Formula: see text]fF to tens of femto farads.

scholarly journals Ultra‐low voltage, power efficient continuous‐time filters in 180 nm CMOS technology

2019 ◽  
Vol 13 (7) ◽  
pp. 988-997
Author(s):  
Rekha S. ◽  
Vasantha Moodabettu Harishchandra ◽  
Tonse Laxminidhi
Keyword(s):  
Continuous Time ◽  
Low Voltage ◽  
Cmos Technology ◽  
Power Efficient ◽  
Continuous Time Filters

Dendron engineering in self-host blue iridium dendrimers towards low-voltage-driving and power-efficient nondoped electrophosphorescent devices

2017 ◽  
Vol 53 (1) ◽  
pp. 180-183 ◽  
Author(s):  
Yang Wang ◽  
Shumeng Wang ◽  
Junqiao Ding ◽  
Lixiang Wang ◽  
Xiabin Jing ◽  
...  
Keyword(s):  
Energy Level ◽  
Low Voltage ◽  
Hole Injection ◽  
Homo Energy ◽  
Power Efficient ◽  
Homo Energy Level

Low-voltage-driving and power-efficient nondoped electrophosphorescent devices have been realized by increasing the dendron's HOMO energy level to favor effective hole injection and promote exciton formation.

Low-voltage power-efficient BiDPL adder for VLSI applications

1999 ◽  
Vol 30 (2) ◽  
pp. 193-197 ◽  
Author(s):  
Martin Margala ◽  
Nelson G Durdle
Keyword(s):  
Low Voltage ◽  
Power Efficient

scholarly journals A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Nabihah Ahmad ◽  
Rezaul Hasan
Keyword(s):  
Circuit Design ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Cmos Process ◽  
Xor Gate ◽  
Power Efficient ◽  
Pass Transistor ◽  
Full Swing

A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.

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