scholarly journals A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Nabihah Ahmad ◽  
Rezaul Hasan
Keyword(s):  
Circuit Design ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Cmos Process ◽  
Xor Gate ◽  
Power Efficient ◽  
Pass Transistor ◽  
Full Swing

A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 547-553
Author(s):  
S. M. Rezaul Hasan ◽  
Yufridin Wahab
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Low Voltage ◽  
Logic Gates ◽  
Base Layer ◽  
Cmos Process ◽  
Silicon Area ◽  
Dynamic Power ◽  
Analog Cmos ◽  
Power Delay Product

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

scholarly journals Design of voltage level shifter for power-efficient applications using 45nm technology

2018 ◽  
Vol 7 (2.8) ◽  
pp. 103
Author(s):  
P Sahithi ◽  
K Hari Kishore ◽  
E Raghuveera ◽  
P Gopi Krishna
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Average Power ◽  
Current Mirror ◽  
Input Frequency ◽  
Voltage Level ◽  
Power Efficient ◽  
Voltage Range ◽  
Level Shifter ◽  
Simulation Results

The paper describes a voltage level shifter for power efficient applications which is simulated in tanner spice tool using 45nm technology. The conservative voltage level shifter is designed by using 6 transistors. The voltage level shifter cell generally used for shifting the voltage range of the signal from one voltage domain to another. This is required when the chip operate at multiple voltage domains. The circuit parameters like leakage voltage and average power dissipation are calculate for this circuit. Mainly level shifter consists of two voltage levels. One is low logic supply voltage (VDDL) another one is high logic supply voltage (VDDH). The simulation results of proposed level shifter with Wilson current mirror by 45nm technology for the input frequency of 1MHZ, the power dissipation of 0.177nW with 3db gain of 9.78.

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