A New Low Voltage Low Power Consumption Comparator for Successive Approximation Register ADCs

2012 ◽  
pp. 205-213
Author(s):  
Shitong Yuan ◽  
Hai Huang ◽  
Qiang Li
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Low Voltage ◽  
Low Power Consumption ◽  
Successive Approximation Register

Low-Voltage Interface Technology for CGS TFT-LCD with Low Power Consumption

1999 ◽  
Vol 30 (1) ◽  
pp. 1116 ◽  
Author(s):  
Y. Kubota ◽  
H. Washio ◽  
K. Maeda ◽  
M. Hijikigawa ◽  
S. Yamazaki
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Low Power Consumption

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

Low Voltage and High Oscillation Frequency Gated Ring Oscillator Using Bootstrap Technique

2013 ◽  
Vol 596 ◽  
pp. 195-198
Author(s):  
Nobukazu Takai ◽  
Ken Murakami ◽  
Haruo Kobayashi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Frequency ◽  
Oscillation Frequency ◽  
Low Voltage ◽  
Ring Oscillator ◽  
Low Power Consumption ◽  
High Oscillation ◽  
High Oscillation Frequency ◽  
Boot Strap

In this paper, a high frequency ring oscillator with low power consumption is proposed.The proposed ring oscillator is based on GRO by applying boot strap technique. Simulation resultsindicate that the FoM(Power Consumption/Oscillation Frequency) of the proposed ring oscillator isless than that of the conventional ring oscillator.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

Using Dual-Channel D/A Converters Design Successive Approximation A/D Converter

2015 ◽  
Vol 719-720 ◽  
pp. 611-614
Author(s):  
Jia Rong Wang ◽  
Xiao Dong Xia ◽  
Zong Da Zhang ◽  
Han Yang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Low Cost ◽  
Electronic Devices ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Digital Converter ◽  
Analog To Digital ◽  
Dual Channel

The successive approximation analog-to-digital converter (ADC) has been widely used in electronic devices due to the corresponding characteristics which are low cost, low power consumption, high accuracy and so on. This paper expounds a design of successive approximation A / D converter to show how to use TCL5615 which is a dual-channel serial 10-bit D/A converter (DAC) to make the conversion accuracy to reach 14-bit.

Low-Power Capacitor-Splitting DAC with Mixed Switching Schemes for SAR ADCs

2018 ◽  
Vol 27 (10) ◽  
pp. 1850161 ◽  
Author(s):  
Hao Wang ◽  
Lungui Zhong ◽  
Guocheng Zhang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Switching Scheme ◽  
Successive Approximation Register ◽  
Switching Power ◽  
Switching Energy ◽  
Switching Method ◽  
Analogue To Digital

A low-power capacitor-splitting digital-to-analogue converter (DAC) for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. During the first three bit cycles, with proper switching, there is no average switching power consumption. From the fourth bit cycle, one-side double-level switching scheme or the monotonic one is utilized based on the first two bits. When the first two bits are the same, one-side double-level switching scheme is chosen. Otherwise, the monotonic one is adopted. Thus, the proposed switching method only requires 5.27 CV[Formula: see text] average switching energy, 75.29% less compared to the Sanyal and Sun proposed one.

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