scholarly journals When Fault Injection Collides with Hardware Complexity

Author(s):  
Sebanjila Kevin Bukasa ◽  
Ludovic Claudepierre ◽  
Ronan Lashermes ◽  
Jean-Louis Lanet
Author(s):  
Sharath Kumar Y. N. ◽  
Dinesha P.

Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.


Author(s):  
Rommel Estores ◽  
Karo Vander Gucht

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.


Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.


Author(s):  
Arvind Kakria ◽  
Trilok Chand Aseri

Background & Objective: Wireless communication has immensely grown during the past few decades due to significant demand for mobile access. Although cost-effective as compared to their wired counterpart, maintaining good quality-of-service (QoS) in these networks has always remained a challenge. Multiple-input Multiple-output (MIMO) systems, which consists of multiple transmitter and receiver antennas, have been widely acknowledged for their QoS and transmit diversity. Though suited for cellular base stations, MIMO systems are not suited for small-sized wireless nodes due to their hardware complexity, cost, and increased power requirements. Cooperative communication that allows relays, i.e. mobile or fixed nodes in a communication network, to share their resources and forward other node’s data to the destination node has substituted the MIMO systems nowadays. To harness the full benefit of cooperative communication, appropriate relay node selection is very important. This paper presents an efficient single-hop distributed relay supporting medium access control (MAC) protocol (EDSRS) that works in the single-hop environment and improves the energy efficiency and the life of relay nodes without compensating the throughput of the network. Methods: The protocol has been simulated using NS2 simulator. The proposed protocol is compared with energy efficient cooperative MAC protocol (EECOMAC) and legacy distributed coordination function (DCF) on the basis of throughput, energy efficiency, transmission delay and an end to end delay with various payload sizes. Result and Conclusion: The result of the comparison indicates that the proposed protocol (EDSRS) outperforms the other two protocols.


Author(s):  
Etienne Boespflug ◽  
Cristian Ene ◽  
Laurent Mounier ◽  
Marie-Laure Potet

2021 ◽  
Vol 120 ◽  
pp. 114116
Author(s):  
Xiaolu Hou ◽  
Jakub Breier ◽  
Dirmanto Jap ◽  
Lei Ma ◽  
Shivam Bhasin ◽  
...  

Author(s):  
Andres Perez-Celis ◽  
Corbin Thurlow ◽  
Michael Wirthlin

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