scholarly journals Fault-Tolerant Computing with Heterogeneous Hardening Modes

2020 ◽  
pp. 161-180
Author(s):  
Florian Kriebel ◽  
Faiq Khalid ◽  
Bharath Srinivas Prabakaran ◽  
Semeen Rehman ◽  
Muhammad Shafique
Keyword(s):  
Fault Tolerant ◽  
Building Blocks ◽  
Soft Error ◽  
Power Efficient ◽  
Heterogeneous Architectures ◽  
Design Choice ◽  
Significant Area ◽  
Computing Platforms ◽  
Comprehensive Reliability ◽  
Dependable Computing

AbstractFault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).

Hybrid Software Redundancy Approach for Building Reliable Communication in Multi-BUS Heterogeneous Systems

2016 ◽  
Vol 23 (04) ◽  
pp. 1650013
Author(s):  
Chafik Arar ◽  
Mohamed Salah Khireddine
Keyword(s):  
Fault Tolerant ◽  
Scheduling Algorithm ◽  
Heterogeneous Systems ◽  
Reliable Communication ◽  
Data Dependencies ◽  
Data Scheduling ◽  
Static Scheduling ◽  
Heterogeneous Architectures ◽  
Multiple Processors ◽  
Hardware Faults

The paper proposes a new reliable fault-tolerant scheduling algorithm for real-time embedded systems. The proposed algorithm is based on static scheduling that allows to include the dependencies and the execution cost of tasks and data dependencies in its scheduling decisions. Our scheduling algorithm is dedicated to multi-bus heterogeneous architectures with multiple processors linked by several shared buses. This scheduling algorithm is considering only one bus fault caused by hardware faults and compensated by software redundancy solutions. The proposed algorithm is based on both active and passive backup copies to minimize the scheduling length of data on buses. In the experiments, the proposed methods are evaluated in terms of data scheduling length for a set of DSP benchmarks. The experimental results show the effectiveness of our technique.

scholarly journals MEASUREMENT-BASED QUANTUM COMPUTATION WITH CLUSTER STATES

2009 ◽  
Vol 07 (06) ◽  
pp. 1053-1203 ◽  
Author(s):  
ROBERT RAUßENDORF
Keyword(s):  
Computational Model ◽  
Quantum Computation ◽  
Quantum Logic ◽  
Network Model ◽  
Quantum Computer ◽  
Fault Tolerant ◽  
Cluster State ◽  
Building Blocks ◽  
Network Simulator ◽  
Classical Level

In this thesis, we describe the one-way quantum computer [Formula: see text], a scheme of universal quantum computation that consists entirely of one-qubit measurements on a highly entangled multiparticle state, i.e. the cluster state. We prove the universality of the [Formula: see text], describe the underlying computational model and demonstrate that the [Formula: see text] can be operated fault-tolerantly. In Sec. 2, we show that the [Formula: see text] can be regarded as a simulator of quantum logic networks. In this way, we prove the universality and establish the link to the network model — the common model of quantum computation. We also indicate that the description of the [Formula: see text] as a network simulator is not adequate in every respect. In Sec. 3, we derive the computational model underlying the [Formula: see text], which is very different from the quantum logic network model. The [Formula: see text] has no quantum input, no quantum output and no quantum register, and the unitary gates from some universal set are not the elementary building blocks of [Formula: see text] quantum algorithms. Further, all information that is processed with the [Formula: see text] is the outcomes of one-qubit measurements and thus processing of information exists only at the classical level. The [Formula: see text] is nevertheless quantum-mechanical, as it uses a highly entangled cluster state as the central physical resource. In Sec. 4, we show that there exist nonzero error thresholds for fault-tolerant quantum computation with the [Formula: see text]. Further, we outline the concept of checksums in the context of the [Formula: see text], which may become an element in future practical and adequate methods for fault-tolerant [Formula: see text] computation.

scholarly journals An Efficient Fault-Tolerant Multi-Bus Data Scheduling Algorithm Based on Replication and Deallocation

2016 ◽  
Vol 16 (2) ◽  
pp. 69-84
Author(s):  
Chafik Arar ◽  
Mohamed Salah Khireddine
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Fault Tolerant ◽  
Scheduling Algorithm ◽  
Experimental Results ◽  
Data Scheduling ◽  
Heterogeneous Architectures ◽  
Hardware Faults

Abstract The paper proposes a new reliable fault-tolerant scheduling algorithm for real-time embedded systems. The proposed scheduling algorithm takes into consideration only one bus fault in multi-bus heterogeneous architectures, caused by hardware faults and compensated by software redundancy solutions. The proposed algorithm is based on both active and passive backup copies, to minimize the scheduling length of data on buses. In the experiments, this paper evaluates the proposed methods in terms of data scheduling length for a set of DAG benchmarks. The experimental results show the effectiveness of our technique.

scholarly journals Engineering the quantum-classical interface of solid-state qubits

2015 ◽  
Vol 1 (1) ◽  
Author(s):  
David J Reilly
Keyword(s):  
Quantum Information ◽  
Solid State ◽  
Degrees Of Freedom ◽  
Technology Development ◽  
Fault Tolerant ◽  
Building Blocks ◽  
Experimental Physicist ◽  
And Mathematics ◽  
Classical Control ◽  
And Control

AbstractSpanning a range of hardware platforms, the building-blocks of quantum processors are today sufficiently advanced to begin work on scaling-up these systems into complex quantum machines. A key subsystem of all quantum machinery is the interface between the isolated qubits that encode quantum information and the classical control and readout technology needed to operate them. As few-qubit devices are combined to construct larger, fault-tolerant quantum systems in the near future, the quantum-classical interface will pose new challenges that increasingly require approaches from the engineering disciplines in combination with continued fundamental advances in physics, materials and mathematics. This review describes the subsystems comprising the quantum-classical interface from the viewpoint of an engineer, experimental physicist or student wanting to enter the field of solid-state quantum information technology. The fundamental signalling operations of readout and control are reviewed for a variety of qubit platforms, including spin systems, superconducting implementations and future devices based on topological degrees-of-freedom. New engineering opportunities for technology development at the boundary between qubits and their control hardware are identified, transversing electronics to cryogenics.

Analyzing the Robustness of HPC Applications Using a Fine-Grained Soft Error Fault Injection Tool

2016 ◽  
pp. 277-305
Author(s):  
Qiang Guan ◽  
Nathan DeBardeleben ◽  
Sean Blanchard ◽  
Song Fu ◽  
Claude H. Davis IV ◽  
...  
Keyword(s):  
High Performance ◽  
Fault Injection ◽  
Soft Errors ◽  
Small Degree ◽  
Soft Error ◽  
Power Efficient ◽  
Fine Grained ◽  
Different Characteristics ◽  
The Impact ◽  
Performance Computing

As the high performance computing (HPC) community continues to push towards exascale computing, HPC applications of today are only affected by soft errors to a small degree but we expect that this will become a more serious issue as HPC systems grow. We propose F-SEFI, a Fine-grained Soft Error Fault Injector, as a tool for profiling software robustness against soft errors. We utilize soft error injection to mimic the impact of errors on logic circuit behavior. Leveraging the open source virtual machine hypervisor QEMU, F-SEFI enables users to modify emulated machine instructions to introduce soft errors. F-SEFI can control what application, which sub-function, when and how to inject soft errors with different granularities, without interference to other applications that share the same environment. We demonstrate use cases of F-SEFI on several benchmark applications with different characteristics to show how data corruption can propagate to incorrect results. The findings from the fault injection campaign can be used for designing robust software and power-efficient hardware.

Semantic Web Services

2009 ◽  
pp. 1293-1298
Author(s):  
Juan Manuel Adán-Coello
Keyword(s):  
Web Services ◽  
Web Service ◽  
Business Processes ◽  
Building Blocks ◽  
Distributed Applications ◽  
Point Of View ◽  
Loosely Coupled ◽  
Service Invocation ◽  
Computing Paradigm ◽  
Computing Platforms

Service-oriented computing (SOC) is a new computing paradigm that uses services as building blocks to accelerate the development of distributed applications in heterogeneous computer environments. SOC promises a world of cooperating services where application components are combined with little effort into a network of loosely coupled services for creating flexible and dynamic business processes that can cover many organizations and computing platforms (Chesbrough & Spohrer, 2006; Papazoglou & Georgakopoulos, 2003). From a technical point of view, the efforts to offer services have focused on the development of standards and the creation of the infrastructure necessary to describe, discover, and access services using the Web. This type of service is usually called a Web service. The availability of an abundant number of Web services defines a platform for distributed computing in which information and services are supplied on demand, and new services can be created (composed) using available services. Nevertheless, the composition of Web services involves three fundamental problems (Sycara, Paolucci, Ankolekar, & Srinivasan, 2003): 1. To elaborate a plan that describes how Web services interact, how the functionally they offer can be integrated to provide a solution to the considered problem. 2. To discover Web services that accomplish the tasks required by the plan. 3. To manage the interaction of the chosen services. Problems 2 and 3 are of responsibility of the infrastructure that supports the composition of services, while the first problem is of responsibility of the (software) agents that use the infrastructure. The discovery and interaction of Web services poses two main challenges to the infrastructure: 1. How to represent Web services capabilities and how to recognize the similarities between service capabilities and the required functionalities. 2. How to specify the information a Web service requires and provides, the interaction protocol, and the low-level mechanisms required to service invocation.

scholarly journals FPGA-Based On-Board Hyperspectral Imaging Compression: Benchmarking Performance and Energy Efficiency against GPU Implementations

2020 ◽  
Vol 12 (22) ◽  
pp. 3741 ◽  
Author(s):  
Julián Caba ◽  
María Díaz ◽  
Jesús Barba ◽  
Raúl Guerra ◽  
Jose A. de la Torre and Sebastián López
Keyword(s):  
Reconfigurable Computing ◽  
Power Efficiency ◽  
Real Life ◽  
Hyperspectral Data ◽  
Actual Behavior ◽  
Power Budget ◽  
Image Block ◽  
Power Efficient ◽  
Time Requirements ◽  
Computing Platforms

Remote-sensing platforms, such as Unmanned Aerial Vehicles, are characterized by limited power budget and low-bandwidth downlinks. Therefore, handling hyperspectral data in this context can jeopardize the operational time of the system. FPGAs have been traditionally regarded as the most power-efficient computing platforms. However, there is little experimental evidence to support this claim, which is especially critical since the actual behavior of the solutions based on reconfigurable technology is highly dependent on the type of application. In this work, a highly optimized implementation of an FPGA accelerator of the novel HyperLCA algorithm has been developed and thoughtfully analyzed in terms of performance and power efficiency. In this regard, a modification of the aforementioned lossy compression solution has also been proposed to be efficiently executed into FPGA devices using fixed-point arithmetic. Single and multi-core versions of the reconfigurable computing platforms are compared with three GPU-based implementations of the algorithm on as many NVIDIA computing boards: Jetson Nano, Jetson TX2 and Jetson Xavier NX. Results show that the single-core version of our FPGA-based solution fulfils the real-time requirements of a real-life hyperspectral application using a mid-range Xilinx Zynq-7000 SoC chip (XC7Z020-CLG484). Performance levels of the custom hardware accelerator are above the figures obtained by the Jetson Nano and TX2 boards, and power efficiency is higher for smaller sizes of the image block to be processed. To close the performance gap between our proposal and the Jetson Xavier NX, a multi-core version is proposed. The results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.

Trust in the Value-Creation Chain of Multimedia Goods

2011 ◽  
pp. 403-424
Author(s):  
Andreas U. Schmidt ◽  
Nicolai Kuntze
Keyword(s):  
Value Creation ◽  
Systematic Approach ◽  
Trusted Computing ◽  
Digital Rights Management ◽  
Building Blocks ◽  
Use Case ◽  
Computing Technology ◽  
Digital Rights ◽  
Rights Management ◽  
Computing Platforms

Security in the value creation chain hinges on many single components and their interrelations. Trusted Platforms open ways to fulfil the pertinent requirements. This chapter gives a systematic approach to the utilisation of trusted computing platforms over the whole lifecycle of multimedia products. This spans production, aggregation, (re)distribution, consumption, and charging. Trusted Computing technology as specified by the Trusted Computing Group provides modular building blocks which can be utilized at many points in the multimedia lifecycle. We propose an according research roadmap beyond the conventional Digital Rights Management use case. Selected technical concepts illustrate the principles of Trusted Computing applications in the multimedia context.

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