Optimized FE Model for System-Level Solder Joint Reliability Analysis of a Flip-Chip Ball Grid Array Package

Author(s):  
Iulia-Eliza Ținca
2008 ◽  
Vol 5 (4) ◽  
pp. 180-187
Author(s):  
Sang Ha Kim ◽  
Chika Kakegawa ◽  
Hiroshi Tabuchi ◽  
Han Park

The major concerns posed by system-in-package (SiP) designs for network applications are the interconnection reliability between the memory plastic ball grid array (PBGA) package and the SiP module, which we refer to as 2nd-level interconnection, and between the SiP module and the system board, which we refer to as 3rd-level interconnection, induced by thermomechanical stress to the large SiP module, i.e., 55 × 55 mm2 package body size. In this paper, finite element analysis (FEA) and design of experiment (DOE) case studies were used to evaluate the 2803-pin flip chip SiP (FCSiP) and to determine the best construction of the SiP module and optimize the assembly material set. Heat spreader (lid) thickness, heat spreader material, and under-fill implementation were considered in the stress and fatigue lifetime FEA case studies and long-term solder joint reliability, which was accelerated thermal cycle (ATC) tested at operating temperatures from 0 to 100°C. Another important factor in the system-level reliability is an external heat sink, and its compressive force effect was also investigated in the ATC test. In addition, short-term mechanical reliability tests, such as the 4-point monotonic bend test based on the IPC-9702 specification and mechanical shock test based on the JESD22-B110A standard, were also evaluated for the 2803-pin FCSiP qualification. Finally, the results of these experiments were compared with the FEA data in a correlation process.


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