Second- and Third-Level BGA Solder Joint Reliability of High-End Flip Chip System in Package (FCSiP)

2008 ◽  
Vol 5 (4) ◽  
pp. 180-187
Author(s):  
Sang Ha Kim ◽  
Chika Kakegawa ◽  
Hiroshi Tabuchi ◽  
Han Park

The major concerns posed by system-in-package (SiP) designs for network applications are the interconnection reliability between the memory plastic ball grid array (PBGA) package and the SiP module, which we refer to as 2nd-level interconnection, and between the SiP module and the system board, which we refer to as 3rd-level interconnection, induced by thermomechanical stress to the large SiP module, i.e., 55 × 55 mm2 package body size. In this paper, finite element analysis (FEA) and design of experiment (DOE) case studies were used to evaluate the 2803-pin flip chip SiP (FCSiP) and to determine the best construction of the SiP module and optimize the assembly material set. Heat spreader (lid) thickness, heat spreader material, and under-fill implementation were considered in the stress and fatigue lifetime FEA case studies and long-term solder joint reliability, which was accelerated thermal cycle (ATC) tested at operating temperatures from 0 to 100°C. Another important factor in the system-level reliability is an external heat sink, and its compressive force effect was also investigated in the ATC test. In addition, short-term mechanical reliability tests, such as the 4-point monotonic bend test based on the IPC-9702 specification and mechanical shock test based on the JESD22-B110A standard, were also evaluated for the 2803-pin FCSiP qualification. Finally, the results of these experiments were compared with the FEA data in a correlation process.

Author(s):  
Kayleen L. E. Helms ◽  
Ketan R. Shah ◽  
Dan Gerbus ◽  
Vasu S. Vasudevan ◽  
Jagadeesh Radhakrishnan ◽  
...  

Increasing power and I/O demands in HDI (high density interconnect) components coupled with the industry-wide conversion to lead-free products has introduced additional risk for solder joint reliability (SJR) of BGA (ball grid array) Flip-Chip electronic packages. One particular concern is SJR under mechanical shock (dynamic bend) loading. While leaded alloys provided good performance in shock for many years due to the unparalleled ability of lead’s slip systems to absorb the energy in shock events, lead-free alloys cannot provide the same benefit. To mitigate this risk, better approaches for understanding damage propagation are needed to enable better design to limit and reduce the SJR risk during shipping and end-user handling. To this end, a characterization study is undertaken to monitor damage progression at the second-level interconnect in BGA’s on flip-chip electronic packages during mechanical shock loading. The study uses a board-level, strain-monitoring approach plus the dye and peel failure analysis technique to track the initiation and propagation of solder joint cracks under loading. The approach being used differs from conventional reliability testing in that both design and load variables are used to quantify damage growth and strain response to bridge the understanding of design feature impact to traditional reliability testing. The scope of the study includes investigating the impact of such factors as package placement, board layout, and enabling load on the monitored board strain and the damage propagation observed. From this study, directions and design guidelines for improving solder joint reliability of future BGA’s on flip-chip electronic packages under mechanical shock loading conditions are proposed.


2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman

2006 ◽  
Vol 504 (1-2) ◽  
pp. 426-430 ◽  
Author(s):  
Dae-Gon Kim ◽  
Jong-Woong Kim ◽  
Seung-Boo Jung

Sign in / Sign up

Export Citation Format

Share Document